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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. features ? 512 channel x 512 channel non-blocking switch at 2.048 mbps, 4.096 mbps or 8.192 mbps operation ? rate conversion between the st-bus inputs and st-bus outputs ? integrated digital phase-locked loop (dpll) meets telcordia gr-1244-core stratum 4 enhanced specifications ? dpll provides automatic reference switching, jitter attenuation, holdover and free run functions ? per-stream st-bus input with data rate selection of 2.048 mbps, 4.096 mbps or 8.192 mbps ? per-stream st-bus output with data rate selection of 2.048 mbps, 4.096 mbps or 8.192 mbps; the output data rate can be different than the input data rate ? per-stream high impedance control output for every st-bus output with fractional bit advancement ? per-stream input channel and input bit delay programming with fractional bit delay ? per-stream output channel and output bit delay programming with fractional bit advancement ? multiple frame pulse outputs and reference clock outputs ? per-channel constant throughput delay ? per-channel high impedance output control ? per-channel message mode ? per-channel pseudo random bit sequence (prbs) pattern generation and bit error detection ? control interface compatible to motorola non- multiplexed cpus ? connection memory block programming capability ? ieee-1149.1 (jtag) test port ? 3.3 v i/o with 5 v tolerant input july 2004 ordering information zl50010/qcc 160 pin lqfp zl50010/gdc 144 ball lbga -40 c to +85 c zl50010 flexible 512 channel dx with enhanced dpll data sheet figure 1 - zl50010 functional block diagram zarlink semiconductor us patent no. 5,602,884, uk patent no. 0772912, france brevete s.g.d.g. 077291 2; germany dbp no. 69502724.7-08 ds cs r/w a11 - 0 dta d15 - 0 test port microprocessor interface v ss v dd tdi tdo tck trst tms sto0-15 reset connection memory cko1 sti0-15 apll fpo1 ode input timing data memory s/p converter p/s converter output hiz control stohz0-15 cko0 fpo0 cko2 fpo2 cki fpi osc xtalo xtali dpll pri_ref and internal registers output timing sg1 tm1 tm2 clkbyps ic0 - 4 sec_ref v ss_apll v dd_apll
zl50010 data sheet 2 zarlink semiconductor inc. applications ? small and medium digital switching platforms ? access servers ? time division multiplexers ? computer telephony integration ? digital loop carriers description the device has 16 st-bus inputs (sti0-15) and 16 st-bus outputs (sto0-15). it is a non-blocking digital switch with 512 64 kbps channels and performs rate conversi on between the st-bus inputs and st-bus outputs. the st-bus inputs accept serial input data streams with the data rate of 2. 048 mbps, 4.096 mbps or 8.192 mbps on a per-stream basis. the st-bus outputs deliver serial output data streams wi th the data rate of 2.048 mbps, 4.096 mbps or 8.192 mbps on a per-stream basis. the device also provid es 16 high impedance control outputs (stohz 0-15) to support the use of ex ternal high impedance control buffers. the zl50010 has features that are programmable on a pe r-stream or per-channel ba sis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control. the on-chip dpll meets telcordia gr- 1244-core stratum 4 enhanced specific ations (stratum 4e). it accepts two dedicated timing reference inputs at either 8 khz, 1.544 mhz or 2.048 mhz . alternatively, one reference can be replaced by an internal 8 khz signal derived from the st -bus input frame boundary. the dpll provides automatic reference switching, jitter attenuation, holdover and free run functions. it can be used as a system?s st-bus timing source which is synchronized to the network. the dp ll can also be bypassed so that the device operates under system timing.
zl50010 data sheet table of contents 3 zarlink semiconductor inc. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 st-bus input data rate and input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 st-bus input operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.2 frame pulse input and clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.3 st-bus input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 st-bus output data rate and output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 st-bus output operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.2 frame pulse output and clock output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.2.3 st-bus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 serial data input delay and serial data output offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.1 input channel delay programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.2 input bit delay programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.3 fractional input bit delay programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.4 output channel delay programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.5 output bit delay programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.6 fractional output bit advancement programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 2.3.7 external high impedance control, stohz 0 to 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 2.4 data delay through the switching paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5 connection memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5.1 connection memory block programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.6 bit error rate (ber) test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.7 quadrant frame programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.8 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.9 digital phase-locked loop (dpll) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.9.1 dpll master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.9.1.1 master mode reference inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.9.1.2 master mode reference switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.9.1.3 dpll status reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.9.1.4 master mode output offset adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.9.2 dpll freerun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.9.3 dpll bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.10 dpll functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.10.1 cki/fpi synchronizer and pri_ref select mux circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.10.2 reference select and frequency mode mux circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.10.3 skew control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.10.4 reference monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.10.5 los control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.10.6 state machine circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.10.7 maximum time interval error (mtie) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.10.8 phase-locked loop (pll) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.11 dpll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.11.1 intrinsic jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.11.2 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.11.3 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.11.4 frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.11.5 holdover accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.11.6 locking range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.11.7 phase slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
zl50010 data sheet table of contents 4 zarlink semiconductor inc. 2.11.8 mtie. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.11.9 phase lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.12 alignment between input and output frame pulses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.0 oscillator requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1 external crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 external clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.0 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.0 jtag support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 test data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4 bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.0 register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.0 detail register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.0 memory address mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.0 connection memory bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
zl50010 data sheet list of figures 5 zarlink semiconductor inc. figure 1 - zl50010 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - 24 mm x 24 mm lqfp (jedec ms-026) pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3 - 13 mm x 13 mm 144 ball lbga pinout diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4 - input timing when (ckin2 to ckin0 bits = 010) in the control register . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5 - input timing when (ckin2 to ckin0 bits = 001) in the control register . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6 - input timing when (ckin2 to ckin0 bits = 000) in the control register . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7 - st-bus input timing for various input data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8 - fpo0 and cko0 output timing when the ckfp0 bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9 - fpo0 and cko0 output timing when the ckfp0 bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10 - fpo1 and cko1 output timing when the ckfp1 bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11 - fpo1 and cko1 output timing when the ckfp1 bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12 - fpo2 and cko2 output timing when the ckfp2 bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13 - fpo2 and cko2 output timing when the ckfp2 bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14 - st-bus output timing for various output data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15 - input channel delay timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16 - input bit delay timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17 - output channel delay timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18 - output bit delay timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19 - fractional output bit advancement timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20 - example: external high impedance control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21 - data throughput delay w hen input and output channel delay are di sabled for input ch0 switched to output ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 22 - data throughput delay when input channel delay is enabled and output channel delay is disabled for input ch0 switched to output ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23 - data throughput delay when input channel delay is disabled and output channel delay is enabled for input ch0 switch to output ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 24 - data throughput delay when input and out put channel delay are enabled for input ch0 switched to output ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 25 - dpll functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 26 - skew control circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 27 - state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 28 - block diagram of the pll module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 29 - dpll jitter transfer function diagram - wide range of frequencies . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 30 - detailed dpll jitter transfer function diagram (wa nder transfer diagram) . . . . . . . . . . . . . . . . . . 41 figure 31 - crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 32 - external clock oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 33 - frame pulse input and clock input timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 34 - frame boundary timing with input clock (cycle-to-cycle) variation . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 35 - frame boundary timing with input frame pulse (cycle -to-cycle) variation. . . . . . . . . . . . . . . . . . . . 73 figure 36 - xtali input timing diagram when clock oscillator is connected . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 37 - reference input timing diagram when the input frequency = 8 khz . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 38 - reference input timing diagram when the input frequency = 2.048 mhz. . . . . . . . . . . . . . . . . . . . . 74 figure 39 - reference input timing diagram when the input frequency = 1.544 hz . . . . . . . . . . . . . . . . . . . . . . 74 figure 40 - input and output frame boundary offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 41 - fpo0 and cko0 timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 42 - fpo1 and cko1 timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 43 - fpo2 and cko2 timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 44 - st-bus inputs (sti0 - 15) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 45 - st-bus outputs (sto0 - 15) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
zl50010 data sheet list of figures 6 zarlink semiconductor inc. figure 46 - serial output and external control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 47 - output driver enable (ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 48 - motorola non-multiplexed bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 49 - jtag test port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 50 - reset pin timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
zl50010 data sheet list of tables 7 zarlink semiconductor inc. table 1 - fpi and cki input programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2 - fpo0 and cko0 output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3 - fpo1 and cko1 output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4 - fpo2 and cko2 output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5 - variable range for input streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6 - variable range for output streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7 - data throughput delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8 - connection memory in block programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9 - definition of the four quadrant frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10 - quadrant frame 0 lsb replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11 - quadrant frame 1 lsb replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12 - quadrant frame 2 lsb replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13 - quadrant frame 3 lsb replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14 - dpll operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15 - los outputs in the failure detect modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16 - address map for device specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 17 - control register (cr) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 18 - internal mode selection (ims) register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 19 - ber start receiving register (bsrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 20 - ber length register (blr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 21 - ber count register (bcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 22 - dpll operation mode (dom) register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23 - dpll output adjustment (dpoa) register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 24 - dpll house keeping (dhkr) register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 25 - stream input control register 0 to 7 (sicr0 to sicr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 26 - stream input control register 8 to 15 (sicr8 to sicr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 27 - stream input delay register 0 to 7 (sidr0 to sidr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 28 - stream input delay register 8 to 15 (sidr8 to sidr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 29 - stream output control register 0 to 7 (socr0 to so cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 30 - stream output control register 8 to 15 (socr8 to socr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 31 - stream output offset register 0 to 7 (soor0 to soor 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 32 - stream output offset register 8 to 15 (soor8 to soor 15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 33 - address map for memory locations (512x512 dx, msb of address = 1). . . . . . . . . . . . . . . . . . . . . . . 68 table 34 - connection memory bit assignment when the cmm bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 35 - connection memory bits assignment when the cmm bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
zl50010 data sheet 8 zarlink semiconductor inc. figure 2 - 24 mm x 24 mm lqfp (jedec ms-026) pinout diagram a0 a2 a3 a10 sti0 sti1 sti8 sti9 vss stohz 15 nc ic2 sto0 vdd fpo1 cko1 vdd ic1 sti10 reset tdo d9 d8 vss nc sg1 tm1 tm2 ode 160 pin lqfp 103 104 106 108 109 110 111 112 113 95 96 94 97 98 99 100 101 102 114 116 117 118 92 91 90 115 93 89 107 105 119 120 135 136 138 140 141 142 143 144 145 127 128 126 129 130 131 132 133 134 146 148 149 150 124 123 122 147 125 121 139 137 151 152 58 57 55 53 52 51 50 49 48 66 65 67 64 63 62 61 60 59 47 45 44 43 69 70 71 46 68 72 54 56 42 41 18 17 15 13 12 11 10 9 8 26 25 27 24 23 22 21 20 19 7 5 4 3 29 30 31 6 28 32 14 16 2 1 cs r/w a5 vdd_apll a6 a7 a8 sti4 sti5 sti6 sti7 sti13 sti14 d12 d11 stohz 12 sto15 sto13 d10 ic3 d2 d14 d13 d3 87 88 86 84 83 82 85 81 d4 34 33 35 37 38 39 36 40 vss xtalo xtali vss ic0 153 154 156 157 158 155 159 160 d5 nc1 nc2 74 73 75 77 78 79 76 80 sti12 sti11 a4 nc sti3 sti2 a9 ds d15 d6 d7 stohz 13 stohz 14 sto12 vdd cko2 fpo2 sti15 dta nc vdd cko0 fpo0 nc d1 (top view) 24 mm x 24 mm 0.5mm pin pitch vss vss vdd d0 vss vdd vss vdd vss vdd vss vdd vss nc nc nc nc nc vss vdd stohz 11 stohz 8 sto11 sto10 sto9 stohz 9 stohz 10 sto8 vss vdd stohz 7 stohz 4 sto7 sto6 sto5 stohz 5 stohz 6 sto4 stohz 3 stohz 0 sto3 sto2 stohz 1 stohz 2 nc nc clkbyps vss_apll nc nc nc nc sto1 a11 nc vdd vss pri_ref sec_ref sto14 vdd vdd vss tdi trst tck tms cki fpi vss a1 vdd jedec ms-026 ic4
zl50010 data sheet 9 zarlink semiconductor inc. figure 3 - 13 mm x 13 mm 144 ball lbga pinout diagram pinout diagram: (as viewed through top of package) a1 corner identified by metallized marking, mould indent, ink dot or right-angled corner 123456789101112 a ode fpo2 fpo0 sec_ ref ic1 ic0 xtali xtalo tm1 cki tdi tck b cko2 cko1 fpo1 cko0 ic3 ic2 clk byps vdd_ apll sg1 fpi trst tms c s to 2 s to 1 s t o h z 0 pri_ ref nc nc ic4 nc2 nc1 tm2 tdo sti15 d s to 3 s to 0 s t o h z 1 vss vdd vdd vdd vss_ apll vss sti8 reset sti14 e s to 5 s to 4 s t o h z 3 stohz 2 vss vss vss vss vdd sti9 sti13 sti12 f s to 6 s to 7 s t o h z 4 vdd vss vss vss vss vdd sti7 sti10 sti11 gstohz 6 stohz 7 stohz 5 vdd vss vss vss vss sti1 sti6 sti5 sti4 h sto9 sto10 sto8 vdd vss vss vss vss sti0 ds sti2 sti3 jsto11stohz 11 stohz 8 vss d2 vdd vdd vdd a10 a9 a8 a11 kstohz 9 stohz 15 sto15 stohz 13 d1 d5 cs d10 d11 a5 a4 a7 lstohz 10 sto12 sto13 d3 d15 d4 d7 d12 d14 a2 a3 a6 msto14stohz 12 stohz 14 d0dtad6d8d9d13a0a1r/w
zl50010 data sheet 10 zarlink semiconductor inc. pin description lqfp pin number lbga ball number name description 10, 23, 33, 43, 48, 58, 68, 78, 92, 102, 113, 127, 136, 146, 156 d5, d6, d7 e9 f4, f9 g4 h4 j6, j7, j8 v dd power supply for the device: +3.3 v 9, 18, 21, 32, 38, 47, 57, 67, 77, 91, 101, 112, 126, 135, 145, 155 d4, d9 e5, e6, e7, e8 f5, f6, f7, f8 g5, g6, g7, g8 h5, h6, h7, h8 j4 v ss (gnd) ground. 3b12 tms test mode select (3.3 v tolera nt input with internal pull- up): jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an internal pull-up resistor when it is not driven. 4a12 tck test clock (5 v tolerant input): provides the clock to the jtag test logic. 5b11 trst test reset (3.3 v tolerant i nput with internal pull-up): asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. when jtag is not being used, this pin should be pulled low during normal operation. 6a11 tdi test serial data in (3.3 v tolerant input with internal pull- up): jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up resistor when it is not driven. 7b10 fpi st-bus frame pulse input (5 v tolerant input): this pin accepts the frame pulse which stays low for 61 ns, 122 ns or 244 ns at the frame boundary. the frame pulse associating with the highest input data rate has to be applied to this pin. the frame pulse frequency is 8 khz. the device also accepts positive frame pulse if the fpin p bit is high in the internal mode selection register. 8a10 cki st-bus clock input (5 v tolerant input): this pin accepts an 4.096 mhz, 8.192 mhz or 16.384 mhz clock. the input clock frequency has to be equal to or greater than twice of the highest input data rate. the clock falling edge defines the input frame boundary. the device also allows the clock rising edge to define the frame boundary by programming the ckinp bit in the internal mode selection register. 11 b9 sg1 apll test control (3.3 v input with internal pull-down): for normal operation, this input must be low.
zl50010 data sheet 11 zarlink semiconductor inc. 12 a9 tm1 apll test pin 1: for normal operation, this input must be low. 13 c10 tm2 apll test pin 2: for normal operation, this input must be low. 14, 15 c9, c8 nc1, nc2 no connection: these pins must be left unconnected. 16 d8 v ss_apll ground for the apll circuit. 17 b8 v dd_apll power supply for the on-chip analog phase-locked loop (apll) circuit: +3.3 v 19 a8 xtalo oscillator clock output (3.3 v output). this pin is connected to a 20 mhz crystal (see figure 31 on page 44), or it is left unconnected if a clock oscillator is connected to the xtali pin (see figure 32 on page 45). if the device is to be used in dpll bypass mode only, the crystal or clock oscillator can be omitted, in which case this pin must be left unconnected. 20 a7 xtali oscillator clock input (3.3 v input). this pin is connected to a 20 mhz crystal (see figure 31 on page 44), or it is connected to a clock oscillator (see figure 32 on page 45). if the device is to be used in dpll bypass mode only, the crystal or clock oscillator can be omitted, in whic h case this pin must be held low. 22 b7 clkbyps test clock input: for device testing only, in normal operation, this input must be low. 24 - 28 a6, a5, b6, b5, c7 ic0 - 4 internal connection (3.3 v tolerant inputs with internal pull-down): in normal mode, these pins must be low. 30 c4 pri_ref primary reference input (5 v tolerant input): this pin accepts an 8 khz, 1.544 mhz or 2.048 mhz timing reference. it is used as one of the primary references for the dpll in the master mode. this pin is ignored in the dpll freerun or bypass mode. when this pin is not in use, it is required to be driven high or low by connecting it to vdd or ground through an external pull- up resistor or external pull-down resistor. 31 a4 sec_ref secondary reference input (5 v tolerant inputs): this pins accept an 8 khz, 1.544 mhz or 2.048 mhz timing reference. it is used as the secondary reference for the dpll in the master mode. this pin is ignored in the dpll freerun or bypass mode. when this pin is not in use, it is required to be driven high or low by connecting it to vdd ground, through an external pull-up resistor or external pull-down resistor. pin description (continued) lqfp pin number lbga ball number name description
zl50010 data sheet 12 zarlink semiconductor inc. 34 a3 fpo0 st-bus frame pulse output 0 (5 v tolerance three-state output): st-bus frame pulse output which stays low for 244 ns or 122 ns at the output frame boundary. its frequency is 8 khz. the polarity of this signal can be changed using the internal mode selection register. 35 b4 cko0 st-bus clock output 0 (5 v tolerant three-state output): a 4.094 mhz or 8.192 mhz clock output. the clock falling edge defines the output frame boundar y. the polarity of this signal can be changed using the inter nal mode selection register. 36 b3 fpo1 st-bus frame pulse output 1 (5 v tolerant three-state output): st-bus frame pulse output which stays low for 61 ns or 122 ns at the output frame boundary. its frequency is 8 khz. the polarity of this signal can be changed using the internal mode selection register. 37 b2 cko1 st-bus clock output 1 (5 v tolerant three-state output): a 16.384 mhz or 8.192 mhz clock output. the clock falling edge defines the output frame boundary. the polarity of this signal can be changed using the internal mode selection register. 44 a2 fpo2 st-bus frame pulse output 2 (5 v tolerant high speed three-state output): st-bus frame pulse output which stays low for 30 ns or 61 ns at the frame boundary. its frequency is 8 khz. the polarity of this signal can be changed using the internal mode selection register. 45 b1 cko2 st-bus clock output 2 (5 v tolerant high speed three- state output): a 32.768 mhz or 16.384 mhz clock output. the clock falling edge defines the output frame boundary. the polarity of this signal can be changed using the internal mode selection register. 46 a1 ode output drive enable (5 v tolerant input): this is the asynchronously output enable control for the sto0 - 15 and the output driven high control for the stohz 0 - 15 serial outputs. when it is high, the sto0 - 15 and stohz 0 - 15 are enabled. when it is low, the sto0 - 15 are in the high impedance state and the stohz 0 - 15 are driven high. 49 - 52 59 - 62 69 - 72 83 - 86 d2, c2, c1, d1 e2, e1, f1, f2 h3, h1, h2, j1 l2, l3, m1, k3 sto0 - 3 sto4 - 7 sto8 - 11 sto12 - 15 serial output streams 0 to 15 (5 v tolerant three-state outputs): the data rate of these output streams can be selected independently using the stream control output registers. in the 2.048 mbps mode , these pins have serial tdm data streams at 2.048 mbps with 32 channels per stream. in the 4.096 mbps mode, these pins have serial tdm data streams at 4.096 mbps with 64 channels per stream. in the 8.192 mbps mode, these pins have serial tdm data streams at 8.192 mbps with 128 channels per stream. pin description (continued) lqfp pin number lbga ball number name description
zl50010 data sheet 13 zarlink semiconductor inc. 53 - 56 63 - 66 73 - 76 87 - 90 c3, d3, e4, e3 f3, g3, g1, g2 j3, k1, l1, j2 m2, k4, m3, k2 stohz 0 - 3 stohz 4 - 7 stohz 8 - 11 stohz 12 -15 serial output streams high impedance control 0 to 15 (5 v tolerant three-state outputs): these pins are used to enable (or disable) external three- state buffers. when an output channel is in the high impedance state, the stohz drives high for the duration of the corres ponding output channel. when the sto channel is active, the stoh z drives low for the duration of the corresponding output channel. 93 - 96 97 - 100 103 - 106 107 - 110 m4, k5, j5, l4 l6, k6, m6, l7 m7, m8, k8, k9 l8, m9, l9, l5 d0 - d3 d4 - d7 d8 - d11 d12 - d15 data bus 0 - 15 (5 v tolerant i/os): these pins form the 16 bit data bus of the microprocessor port. 111 m5 dta data transfer acknowledgme nt (5 v tolerant three-state output): this active low output indicates that a data bus transfer is complete. a pull-up resistor is required to hold this pin at high level. 114 k7 cs chip select (5 v tolerant input): active low input used by the microprocessor to enable t he microprocessor port access. 115 m12 r/w read/write (5 v tolerant input): this input controls the direction of the data bus lines (d0-d15) during a microprocessor access. 116 h10 ds data strobe (5 v tolerant input): this active low input works in conjunction with cs to enable the microprocessor port read and write operations. 117, 118 123 - 125 128 - 130 131 - 134 m10, m11 l10, l11, k11 k10, l12, k12 j11, j10, j9, j12 a0 - a1 a2 - a4 a5 - a7 a8 - a11 address 0 - 11 (5 v tolerant inputs): these pins form the 12 bit address bus to the inter nal memories and registers. 137 - 139 140 - 142 143, 144 147 - 149 150 - 152 153, 154 h9, g9, h11 h12, g12, g11 g10, f10 d10, e10, f11 f12, e12, e11 d12, c12 sti0 - 2 sti3 - 5 sti6 - 7 sti8 - 10 sti11- 13 sti14 - 15 serial input streams 0 to 15 (5 v tolerant inputs): the data rate of these input str eams can be selected independently using the stream input contro l registers. in the 2.048 mbps mode, these pins accept serial tdm data streams at 2.048 mbps with 32 channels per stream. in the 4.096 mbps mode, these pins accept serial tdm data streams at 4.096 mbps with 64 channels per stream. in the 8.192 mbps mode, these pins accept serial tdm data streams at 8.192 mbps with 128 channels per stream. unused serial input pins are re quired to connect to either vdd or ground, through an external pu ll-up resistor or external pull- down resistors. pin description (continued) lqfp pin number lbga ball number name description
zl50010 data sheet 14 zarlink semiconductor inc. 157 d11 reset device reset (5 v tolerant input): this input (active low) puts the device in its reset state that disables the sto0 - 15 drivers and drives the stohz 0 - 15 outputs to high. it also clears the device registers and internal counters. to ensure proper reset action, the reset pin must be low for longer than 1 ms. upon releasing the reset si gnal to the device, the first microprocessor access can take place after 600 s due to the time required to stab ilize the apll and crys tal oscillator blocks from the power down state. 158 c11 tdo test serial data out (3 v tolerant three-state output): jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag is not enabled. 1, 2, 29, 39 - 42, 79 - 82, 119 - 122, 159, 160 c5, c6 nc no connection pins. these pins are not connected to the device internally. pin description (continued) lqfp pin number lbga ball number name description
zl50010 data sheet 15 zarlink semiconductor inc. 1.0 device overview the device uses the st-bus input frame pulse and the st -bus input clock to define the input frame boundary and timing for the st-bus input streams with various data rates (2.048 mbps, 4.096 mbps and/or 8.192 mbps). the output frame boundary is defined by the output frame pulses and the output clock timing for the st-bus output streams with various data rates (2.048 mbps, 4.096 mbps and/or 8.192 mbps). by using zarlink?s message mode capability, microprocessor data can be broadcast to the data output streams on a per channel basis. this feature is useful for transferring control and status in formation for external circuits or other st-bus devices. the on-chip dpll can be operated in one of three modes: master, freerun or bypass. in master mode, the dpll can be used as a system?s timing source to provide st-b us clocks and frame pulses which are synchronized to the network. in freerun mode, the dpll can be used to prov ide system st-bus timing which is independent of the network. in bypass mode, the dpll is completely bypa ssed and the device operates entirely from system timing provided by the input st-bus clock and frame pulse. an ex ternal 20.000 mhz crystal or clock oscillator is required in master and freerun modes. the dpll intr insic jitter is 6.25 ns peak to peak. in master mode, the dpll is synchronized to either the pri_ref input, the sec_ref input, or to an internal 8 khz signal derived from the input st-bus clock and frame pulse. the pri_ref and sec_ref inputs accept 8 khz, 1.544 mhz or 2.048 mhz network timing reference signal s. the dpll also provides reference monitoring, automatic bit-error-free reference sw itching, jitter attenuation and holdov er functions. the dpll output is an internal high speed clock from which output st-bus clock and frame pulses are generated. a non-multiplexed microprocessor port allows users to program the devi ce with various operating modes and switching configurations. user s can use the microprocessor port to perfo rm register read/write, connection memory read/write and data memory read opera tions. the microprocessor port has a 12 bit address bus, a 16 bit data bus and four control signals. the device also supports the mandatory requirements of the ieee-1149.1 (jtag) st andard via the test port. 2.0 functional description a functional block diagram of the zl50010 is shown in figure 1 on page 1. 2.1 st-bus input data rate and input timing the device has 16 st-bus serial data inputs. any of the 16 inputs can be programmed to accept different data rates, 2.048 mbps, 4.096 mbps or 8.192 mbps. 2.1.1 st-bus input operation mode any st-bus input can be programmed to accept the 2.048 mbps, 4.096 mbps or 8.192 mbps data using bit 0 to 2 in the stream input control registers, sicr0 to sicr15 as shown in table 25 on page 58 and table 26 on page 60. the maximum number of input channels is 512 channels. exte rnal pull-up or pull-down resistors are required for any unused st-bus inputs. 2.1.2 frame pulse input and clock input timing the frame pulse input fpi accepts the frame pulse used for the highest input data rate. the frame pulse is an 8 khz input signal which stays low for 244 ns, 122 ns or 61 ns for the input data rate of 2.048 mbps, 4.096 mbps or 8.192 mbps respectively. the frequency of cki must be twice the highest data rate. for example, if users present the zl50010 with 2.048 mbps and 8.192 mbps input data , the device should be progr ammed to accept the input clock of 16.384 mhz and the frame pulse which stays low for 61 ns.
zl50010 data sheet 16 zarlink semiconductor inc. users have to program the ckin2 - 0 bi ts in the control register (cr), for the width of the frame pulse low cycle and the frequency of the input clock. see table 1 for the programming of the ckin0, ckin1 and ckin2 bits in the control register. table 1 - fpi and cki input programming the device also accepts positive or negative input frame pulse and st -bus input clock formats via the programming of the fpinp and ckinp bits in the inter nal mode selection (ims) regi ster. by default, the device accepts the negative input clock format. figure 4, figure 5 and figure 6 describe the usage of ckin 2 - 0, fpinp and ckinp in the internal mode selection (ims) register: figure 4 - input timing when (ckin2 to ckin0 bits = 010) in the control register figure 5 - input timing when (ckin2 to ckin0 bits = 001) in the control register figure 6 - input timing when (ckin2 to ckin0 bits = 000) in the control register ckin2 - 0 bits fpi low cycle cki highest input data rate 000 61 ns 16.384 mhz 8.192 mbps 001 122 ns 8.192 mhz 4.096 mbps 010 244 ns 4.096 mhz 2.048 mbps 011 - 111 reserved input frame boundary input frame boundary fpi (4.096 mhz) cki (8 khz) fpi fpinp = 1 fpinp = 0 ckinp = 0 (4.096 mhz) cki ckinp = 1 input frame boundary (8.192 mhz) cki fpi fpi fpinp = 1 fpinp = 0 (8.192 mhz) cki ckinp = 0 ckinp = 1 input frame boundary (16.384 mhz) cki fpi fpinp = 0 fpi fpinp = 1 ckinp = 0 (16.384 mhz) cki ckinp = 1 input frame boundary input frame boundary
zl50010 data sheet 17 zarlink semiconductor inc. 2.1.3 st-bus input timing when the negative input frame pulse and negative input clock formats are used, the input frame boundary is defined by the falling edge of the cki input clock while the fpi is low. when the input data rate is 2.048 mbps, 4.096 mbps or 8.192 mbps, there are 32, 64 or 128 channels per every st-bus frame respectively. figure 7 shows the details: figure 7 - st-bus input timing for various input data rates fpi (4.096 mhz) cki (8 khz) (8.192 mhz) cki (16.384 mhz) cki 72 3 4 5 610 sti (8.192 mbps) channel 0 72 3 4 5 610 channel 1 2 310 72 3 4 5 610 channel 127 2 3 4 5 610 channel 126 76 fpi input frame boundary 5 6 74 sti (4.096 mbps) channel 0 1 2 30 10 1 2 30 channel 63 5 64 7 76 sti (2.048 mbps) channel 0 54 0 10 channel 31 32 7 fpi input frame boundary
zl50010 data sheet 18 zarlink semiconductor inc. 2.2 st-bus output data rate and output timing the device has 16 st-bus serial data outputs. any of t he 16 outputs can be programmed to deliver different data rates at 2.048 mbps, 4.096 mbps or 8.192 mbps. 2.2.1 st-bus output operation mode any st-bus output can be programmed to deliver the data at 2.048 mbps, 4.096 mbps or 8.192 mbps mode using bit 0 to 2 in the stream output control registers, socr0 to socr15 as shown in table 29 on page 64 and table 30 on page 65. the maximum number of output channels is 512 channels. 2.2.2 frame pulse outp ut and clock output timing the device offers 3 frame pulse outputs, fpo0 , fpo1 and fpo2 . all output frame pulses are 8 khz output signals. by default, the output fram e boundary is defined by the falling edge of the cko0 , cko1 or cko2 output clocks while the fpo0 , fpo1 or fpo2 output frame pulse goes low respectively. in addition to the default settings, user s can also select different output frame pulse low cycles and output clock frequencies by programming the ckfp0, ckfp1 and ckfp2 bi ts in the control register. see table 2, table 3 and table 4 for the bit usage in the control register: ckfp0 fpo0 low cycle cko0 0 244 ns 4.096 mhz 1 122 ns 8.192 mhz table 2 - fpo0 and cko0 output programming ckfp1 fpo1 cko1 0 61 ns 16.384 mhz 1 122 ns 8.192 mhz table 3 - fpo1 and cko1 output programming ckfp2 fpo2 cko2 0 30 ns 32.768 mhz 1 61 ns 16.384 mhz table 4 - fpo2 and cko2 output programming
zl50010 data sheet 19 zarlink semiconductor inc. the device also delivers positive or negative output fr ame pulse and st-bus output clock formats via the programming of the fp0p, fp1p, fp2p, ck0p, ck1p and ck2p bits in the internal mo de selection (ims) register. by default, the device delivers the negative output frame pulse and negative output clock formats. figure 8 to figure 13 describe the us age of the ckfp0, ckfp1, ckfp2, fp0p, fp1p, fp2p, ck0p, ck1p and ck2p in the control register and internal mode selection register: figure 8 - fpo0 and cko0 output timing when the ckfp0 bit = 0 figure 9 - fpo0 and cko0 output timing when the ckfp0 bit = 1 figure 10 - fpo1 and cko1 output timing when the ckfp1 bit = 0 figure 11 - fpo1 and cko1 output timing when the ckfp1 bit = 1 fpo0 (4.096 mhz) cko0 (8 khz) fpo0 fp0p = 1 fp0p = 0 ckop = 0 (4.096 mhz) cko0 ckop = 1 (8.192 mhz) cko0 fpo0 fpo0 fpop =1 fpop = 0 (8.192 mhz) cko0 ckop = 0 ckop = 1 (16.384 mhz) cko1 fpo1 fp1p = 0 fpo1 fp1p = 1 ck1p = 0 (16.384 mhz) cko1 ck1p = 1 (8.192 mhz) cko1 fpo1 fpo1 fp1p =1 fp1p = 0 (8.192 mhz) cko1 ck1p = 0 ck1p = 1
zl50010 data sheet 20 zarlink semiconductor inc. figure 12 - fpo2 and cko2 output timing when the ckfp2 bit = 0 figure 13 - fpo2 and cko2 output timing when the ckfp2 bit = 1 (32.768 mhz) cko2 fpo2 fp2p = 0 fpo2 fp2p = 1 ck2p = 0 (32.768 mhz) cko2 ck2p = 1 (16.384 mhz) cko2 fpo2 fp2p = 0 fpo2 fp2p = 1 ck2p = 0 (16.384 mhz) cko2 ck2p = 1
zl50010 data sheet 21 zarlink semiconductor inc. 2.2.3 st-bus output timing by default, the output frame boundary is defined by the falling edge of the cko0 , cko1 or cko2 output clock while the fpo0 , fpo1 or fpo2 output frame pulse goes low respectively. w hen the output data rates are 2.048 mbps, 4.096 mbps and 8.192 mbps, there are 32, 64 or 128 output channels per ever y st-bus frame respectively. figure 14 describes the details. figure 14 - st-bus output timing for various output data rates fpo0 (4.096 mhz) cko (8 khz) (8.192 mhz) cko0 or cko1 (16.384 mhz) cko1 or cko2 72 3 4 5 610 sto (8.192 mbps) channel 0 72 3 4 5 610 channel 1 2 310 72 3 4 5 610 channel 127 2 3 4 5 610 channel 126 76 fpo0 or fpo1 output frame boundary 5 6 74 sto (4.096 mbps) channel 0 1 2 30 10 1 2 30 channel 63 5 64 7 76 sto (2.048 mbps) channel 0 54 0 10 channel 31 32 7 fpo1 or fpo2 output frame boundary (32.768 mhz) cko2 fpo2
zl50010 data sheet 22 zarlink semiconductor inc. 2.3 serial data input delay and serial data output offset various registers are provided to adju st the input and output delays for every input and every output data stream. the input and output channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 channel(s) for the 2.048 mbps, 4.096 mbps and 8.192 mbps modes respectively. the input and output bit delay can vary from 0 to 7 bits. the fractional input bit delay can vary from 1/4, 1/2, 3/4 to 4/4 bit. the fractional output bit advancem ent can vary from 0, 1/4, 1/2 to 3/4 bit. 2.3.1 input channel delay programming this feature allows each input stream to have a differ ent input frame boundary with respect to the input frame boundary defined by the fpi and cki . by default, all input streams have channel delay of zero such that ch0 is the first channel that appears after t he input frame boundary (see figure 15). the input channel delay programmi ng is enabled by setting bit 3 to 9 in the stream input delay register (sidr). the input channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 for the 2.048 mbps, 4.096 mbps and 8.192 mbps modes respectively. figure 15 - input channel delay timing diagram 2.3.2 input bit delay programming in addition to the input channel delay programming, the input bit delay programming feat ure provides users with more flexibility when designing the switch matrices at hi gh speed, in which the delay lines are easily created on pcm highways which are connected to the switch matrix cards. by default, all input st reams have zero bit delay such that bit 7 is the first bit that appears after the input frame boundary, see figure 16 on page 23. the input delay is enabled by bit 0 to 2 in the stream input delay registers (sidr). the input bit delay can vary from 0 to 7 bits. fpi 72 3 4 5 610 channel delay = 0 ch 0 72 3 4 5 610 ch 1 2 310 72 3 4 5 610 last channel 2 3 4 5 610 last channel -1 76 72 3 4 5 610 channel delay = 1 last channel 72 3 4 5 610 ch 0 2 310 72 3 4 5 610 last channel -1 2 3 4 5 610 last channel -2 76 72 3 4 5 610 channel delay = 2 last channel -1 72 3 4 5 610 last channel 2 310 72 3 4 5 610 last channel -2 2 3 4 5 610 ch0 76 (default) delay = 1 delay = 2 7 sti x sti x sti x note: last channel = 31, 63, 127 for 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively input frame boundary note: x = 0 to 15
zl50010 data sheet 23 zarlink semiconductor inc. 2.3.3 fractional i nput bit delay programming in addition to the input bit delay feat ure, the device allows users to change t he sampling point of the input bit. by default, the sampling point is at 3/4 bi t. users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position by programming bit 3 and 4 of the str eam input control registers (sicr). figure 16 - input bit delay timing diagram 2.3.4 output channel delay programming this feature allows each out put stream to have a different output frame boundary with respect to the output frame boundary defined by the output frame pulse (fpo0 , fpo1 and fpo2 ) and the output clock (cko 0, cko1 or cko2 ). by default, all output streams have zero channel delay such that ch 0 is the first channel that appears after the output frame boundary as shown in figure 17. different ou tput channel delay can be se t by programming bit 5 to 11 in the stream output offset registers (soor). the outpu t channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 for the 2.048 mbps, 4.096 mbps and 8.192 mbps modes respectively. figure 17 - output channel delay timing diagram fpi 72 3 4 5 610 sti x bit delay = 0 ch0 74 5 6 ch1 2 310 72 3 4 5 610 sti x bit delay = 1 ch0 75 6 ch1 2 310 (default) last channel last channel bit delay = 1 note: last channel = 31, 63, 127 for 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively input frame boundary note: x = 0 to 15 4 fpo 72 3 4 5 610 channel delay = 0 ch 0 72 3 4 5 610 ch 1 2 310 72 3 4 5 610 last channel 2 3 4 5 610 last channel -1 76 72 3 4 5 610 channel delay = 1 last channel 72 3 4 5 610 ch 0 2 310 72 3 4 5 610 last channel -1 2 3 4 5 610 last channel -2 76 72 3 4 5 610 channel delay = 2 last channel -1 72 3 4 5 610 last channel 2 310 72 3 4 5 610 last channel -2 2 3 4 5 610 ch0 76 (default) delay = 1 delay = 2 7 sto x sto x sto x note: last channel = 31, 63, 127 for 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively output frame boundary note: x = 0 to 15
zl50010 data sheet 24 zarlink semiconductor inc. 2.3.5 output bit delay programming this feature is used to delay the output data bit of i ndividual output streams with respect to the output frame boundary. each output stream can have its own bit delay value. by default, all output streams have zero bit delay such that bit 7 is the first bit that appears after the output frame boundary (see figure 18 on page 24). different output bit dela y can be set by programming bit 2 to 4 in the stream output offset registers. the output bit delay can vary from 0 to 7 bits. figure 18 - output bit delay timing diagram 2.3.6 fractional output bit advancement programming in addition to the output bit delay, the device is also capable of performing fracti onal output bit advancement. this feature offers a better resolu tion for the output bit delay adjustment. the fractional out put bit advancement is useful in compensating for various parasitic lo adings on the serial data output pins. by default, all output streams have zero fractional bit advanc ement such that bit 7 is t he first bit that appears after the output frame boundary as shown in figure 19. the fr actional output bit advancement is enabled by bit 0 to 1 in the stream output offset registers. the fractional bit advancement can va ry from 0, 1/4, 1/2 or 3/4 bit. figure 19 - fractional output bit advancement timing diagram fpo 72 3 4 5 610 sto x bit delay = 0 ch0 74 5 6 ch1 2 310 72 3 4 5 610 sto x bit delay = 1 ch0 75 6 ch1 2 310 (default) last channel last channel bit delay = 1 note: last channel = 31, 63, 127 for 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively output frame boundary note: x = 0 to 15 4 fpo bit 7 bit 6 sto y fractional bit adv. = 0 ch0 (default) sto y fractional bit adv. = 1/4 bit fractional bit advancement = 1/4 bit bit 7 bit 6 ch0 bit 0 last channel bit 1 bit 0 bit 1 last channel note: last channel = 31, 63, 127 for 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively output frame boundary note: y = 0 to 15
zl50010 data sheet 25 zarlink semiconductor inc. 2.3.7 external high impe dance control, stohz 0 to 15 the stohz 0 to 15 outputs are provided to control the external tristate st-bus drivers for per-channel high impedance operations. the stohz outputs are sent out in 32, 64 or 128 timeslots corresponding to the output channels for 2.048 mbps, 4.096 mbps and 8.192 mbps output streams respectively. each control timeslot lasts for one channel time. when the ode pin is high, the stohz 0 - 15 are enabled. when the ode pin or the reset pin is low, the stohz 0 - 15 are driven high. stohz outputs are also driven hi gh if their corresponding st-bus outputs are not in use. figure 20 gives an example when channel 2 of a given st -bus output is programmed in the high impedance state, the corresponding stohz pin drives high for o ne channel time at the channel 2 timeslot. by default, the output timing of the stohz signals fo llow the same timing as t heir corresponding sto signals including any user-programmed channel and bit delay and fr actional bit advancement. in addition, the device allows users to advance the stohz signals from their default positions to a maximum of four 15.2 ns steps (or four 1/4 bit steps) using bit 3 to 5 of the stream output control register (socr). bit 6 in the stream output control register selects the step resolution as 15.2 ns or 1/4 data bit. the additional advancement feature allows the stohz signals to better match the high impedance timing r equired by the external st-bus drivers. when the device is in dpll master mode (or freerun mode) and the additional stohz advancement is set to zero, there is no phase difference between t he sto0 - 15 and the stohz 0 to 15. when the device is in dpll master mode (or freerun mode) and the additional stohz advance is not zero, the phase correction of 6.25 ns could happen between the sto0 - 15 and stohz 0 to 15 because t hese outputs are clocked by various internal clock edges and the dpll output has the intrinsic jitter of 6.25 ns. when the device is in the dpll bypass mode, there is no phase correction between the sto0 -15 of the stohz 0- 15 regardless whether the additional stohz advancement is enabled or disabled. figure 20 - example: external high impedance control timing output frame boundary ch1 ch0 sto y ch3 ch2 last ch last ch last ch-1 last ch -2 ch0 fpo hiz stohz y note: last channel = 31, 63, 127 for 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively stohz y note: y = 0 to 15 stohz advancement (programmable in 4 steps of 15.2 ns or 1/4 bit) (default = no adv.) (with adv.)
zl50010 data sheet 26 zarlink semiconductor inc. 2.4 data delay through the switching paths to maintain the channel integrity in the constant delay mode, the usage of the input channel delay and output channel delay modes affect the data delay through various switching paths due to additional data buffers. the usage of these data buffers is enabled by the input and output channel delay bits (stin#cd6-0 and sto#cd6-0) in the stream input delay and stream outp ut offset registers. however, the in put and output bit delay or the input and output fractional bit offset have no im pact on the overall data throughput delay. in the following paragraphs, the data throughput delay (t) is expressed as a function of st-bus frames, input channel number (m), output channel number (n), input channel delay ( ) and output channel delay ( ). table 5 describes the variable range for input streams and table 6 describes the vari able range for output streams. table 7 summarizes the data throughput delay under various i nput channel and output channel delay conditions. input stream data rate input channel number (m) possible input channel delay ( ) 2 mbps 0 to 31 1 to 31 4 mbps 0 to 63 1 to 63 8 mbps 0 to 127 1 to 127 table 5 - variable range for input streams output stream data rate output channel number (n) possible output channel delay ( ) 2 mbps 0 to 31 1 to 31 4 mbps 0 to 63 1 to 63 8 mbps 0 to 127 1 to 127 table 6 - variable range for output streams input channel delay off output channel delay off input channel delay on output channel delay off input channel delay off output channel delay on input channel delay on output channel delay on t = 2 frames + (n-m) t = 3 frames - + (n-m) t = frames + + (n-m) t = 3 frames - + + (n-m) table 7 - data throughput delay
zl50010 data sheet 27 zarlink semiconductor inc. by default, when the input channel delay and output c hannel delay are set to zero, the data throughput delay ( t ) is: t = 2 frames + (m-n) . figure 21 shows the throughput delay when the input ch0 is switched to the output ch0. figure 21 - data throughput delay when input and output channel delay are disabled for input ch0 switched to output ch0 when the input channel delay is enabl ed and the output channel delay is disa bled, the data throughput delay is: t = 3 frames - + (m-n) . figure 22 shows the data throughput delay wh en the input ch0 is switched to the output ch0. figure 22 - data throughput delay when input channel delay is enabled and output channel delay is disabled for input ch 0 switched to output ch0 when the input channel delay is di sabled and the output channel delay is enabled, the throughput delay is: t = 2 frames + + (m-n) . figure 23 shows the data throughput delay w hen the input ch0 is swit ched to the output ch0. figure 23 - data throughput delay when input channel delay is disabled and output channel delay is enabled for input ch0 switch to output ch0 frame frame n frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data (no delay) serial output data (no delay) frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + 0 frame frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data ( = 1) serial output data (no delay) frame n-3 data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data serial input data ( > 1) frame n-1 data frame n+4 data frame n input channel delay (from 1 to max# of channels, programmed by the stin#cd6-0 bit) 3 frames - + 0 3 frames - 1 channel + 0 frame frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input (no delay) serial output data ( > 1) frame n-3 data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n serial output data ( = 1) frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + 1 + 0 output channel delay:(from 1 to max# of channels, programmed by the sto#cd6-0 bit) 2 frames + + 0
zl50010 data sheet 28 zarlink semiconductor inc. when the input channel delay and the output channe l delay are enabled, the data throughput delay is: t = 3 frames - + + (m-n) . figure 24 shows the data throughput delay when the input ch0 is switched to the output ch0. figure 24 - data throughput delay when input and output channel delay are enabled for input ch0 switched to output ch0 2.5 connection memory description the connection memory is 12-bit wide. there are 512 memo ry locations to support the st-bus serial outputs sto0-15. the address of each connection memory locati on corresponds to an output destination stream number and an output channel number. see table on page 68 for the connection memory address map. when bit 0 of the connection memory is low , bit 1 to 7 define the source (input) channel address and bit 8 to 11 define the source (input) st ream address. once the sour ce stream and channel addres ses are programmed by the microprocessor, the contents of the data memory at the selected address are switched to the mapped output stream and channel. see table 34 on page 69 for details on the memory bit assignment when bit 0 of the connection memory is low. when bit 0 of the connection memory is high , bit 1 and 2 define the per-channel control modes of the output streams, the per-channel high impedance output contro l, the per-channel message and the per-channel ber test modes. in the message mode, the 8-bit message data loca ted in bit 3 to 10 of the connection memory will be transferred directly to the mapped output stream. see table 35 on page 69 for details on the memory bit assignment when bit 0 of the connection memory is high. 2.5.1 connection memory block programming this feature allows fast initializat ion of the entire connection memory af ter power up. when block programming mode is enabled, the content of bit 1 to 3 in the internal mode selection (ims) register will be loaded into bit 0 to 2 of all the 512 connection memory locations. the other bit positions of the connection memory will be loaded with zeros. frame frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 serial output data ( > 1) frame n-4 data frame n-3 data frame n-2 data frame n-1 data frame n data frame n+1 data frame n serial output data ( = 1) frame n-3 data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data output channel delay:(from 1 to max# of channels, programmed by the sto#cd6-0 bit) frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data ( = 1) frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data seiail input data ( > 1) frame n-1 data frame n+4 data input channel delay:(from 1 to max# of channels, programmed by the stin#cd6-0 bit) 3 frames - 1 + 1 + 0 3 frames - + 1 + 0 3 frames - 1 + + 0 3 frames - + + 0
zl50010 data sheet 29 zarlink semiconductor inc. memory block programming procedure : (assumption: the mbpe and mbps bits are bo th low at the start of the procedure) ? program bit 1 to 3 (bpd0 to bpd2) in the ims (internal mode selection) register. ? set the memory block programming enable (mbpe) bit in the control register to high to enable the block programming mode. ? set the memory block programming start (mbps) bit to high in the ims register to start the block programming. the bpd0 to bpd2 bits will be loaded into bit 0 to 2 of the connection memory. the other bit positions of the connection memory will be loaded with zeros. the memory content after block programming is shown in table 8. ? it takes 50 s for the connection memory to be loaded with the bit pattern defined by the bpd0 to bpd2 bits. ? after loading the bit pattern to the entire connection me mory, the device will reset the mbps bit to low, indicating that the process has finished. ? upon completion of the block programming, set the mbpe bit from high to low to disable the block programming mode. note : once the block programming is started, it can be term inated at any time prior to completion by setting the mbps bit or the mbpe bit to low. if the mbpe bit is used to terminate the block pr ogramming before completion, users have to set the mbps bit from high to low before enabling other device operation. table 8 - connection memory in block programming mode 2.6 bit error rate (ber) test the zl50010 has one on-chip ber transmitter and one ber receiver. the transmitter can transmit onto a single sto output stream only. the transmitter provides a ber sequence (2 15 -1 pseudo random code) which can start from any channel in the frame and lasts from one channel up to one frame time (125 s). the transmitter output channel(s) are specified by programming the connection memory location(s) corresponding to the channel(s) of the selected output stream: bit 0 to 2 of the connection memory location(s) should be programmed to the ber test mode (see table 35 on page 69). multiple connection memory locations can be programme d for ber test such that the ber patterns can be transmitted for several output channels which are consec utive. if the transmitti ng output channels are not consecutive, the ber receiver will no t compare the bit patterns correctly. the number of output channels which t he ber transmitter occupies also has to be the same as the number of channels defined in the ber length register. the ber len gth register defines how many ber channels to be monitored by the ber receiver. registers used for setting up the ber test are as follows: ? control register ( cr ) - the cber bit is used to clear the bit error counter and the ber count register (bcr). the sber bit is used to start or stop the ber transmitter and ber receiver. ? ber start receiving register ( bsrr ) - defines the input stream and channel from where the ber sequence will start to be compared. ? ber length register ( blr ) - defines how many channels the sequence will last. 11109876543210 000000000bpd2bpd1bpd0
zl50010 data sheet 30 zarlink semiconductor inc. ? ber count register ( bcr ) - contains the number of counted errors. when the error count reaches hex ffff, the bit error counter will stop so that it will not overflow. consequently the ber count register will also stop at ffff. the cber bit in the control register is used to reset the bit error counter and the ber count register. as described above, the sber bit in the co ntrol register controls the ber trans mitter and receiver. to carry out the ber test, users should set the sber bit to zero to di sable the ber trans mitter during the programming of the connection memory for the ber test. when the ber transmitt er is disabled, the transmitter output is all ones. hence any output channel whose connection memory has been programmed to ber test mode will also output all ones. upon the completion of programming the connection memory for the ber test, set the sber bit to one to start the ber transmitter and receiver for the ber testi ng. they must be allowed to run for several frames (2 frames plus the network delay between sto and sti) before the ber receiver can correctly identify errors in the pattern. thus after this time the bit error counter should be reset by using the cber bit in the control register - set cber to one then back to zero. from now on, the count will be the actual nu mber of errors wh ich occurred during the test. the count will stop at ffff and the counter will not increment even if more errors occurred. 2.7 quadrant frame programming by programming the input stream control registers (sicr0 to 15), users can divide 1 frame of input data into 4 quadrant frames and can force the leas t significant bit (lsb, bit 0 in figu re 7 on page 17) of every input channel in these quadrants into "1" for the bit robbed signalling purpose. the 4 quadrant frames are defined as shown in table 9. when a quadrant frame enable bit (stin#qen0, stin#qen1, stin#qen2 or stin#qen3) is set to high, the lsb of every input channels in the quadrant is forced to "1". see table 10 to table 13 for details: data rate quadrant 0 quadrant 1 quadrant 2 quadrant 3 2.048 mbps ch 0 to 7 ch 8 to 15 ch 16 to 23 ch 24 to 31 4.096 mbps ch 0 to 15 ch 16 to 31 ch 32 to 47 ch 48 to 63 8.192 mbps ch 0 to 31 ch 32 to 63 ch 64 to 95 ch 96 to 127 table 9 - definition of the four quadrant frames stin#qen0 action 1 replace lsb of every channel in quadrant 0 with "1" 0 no bit replacement occurs in quadrant 0 table 10 - quadrant frame 0 lsb replacement stin#qen1 action 1 replace lsb of every channel in quadrant 1 with "1" 0 no bit replacement occurs in quadrant 1 table 11 - quadrant frame 1 lsb replacement stin#qen2 action 1 replace lsb of every channel in quadrant 2 with "1" 0 no bit replacement occurs in quadrant 2 table 12 - quadrant frame 2 lsb replacement
zl50010 data sheet 31 zarlink semiconductor inc. 2.8 microprocessor port the device supports the non-multiplexed microprocessor. the mi croprocessor port consists of a 16 bit parallel data bus (d0 to 15), a 12 bit address bus (a0 to 11) and four control signals (cs , ds , r/w and dta ). the parallel microprocessor port provides fast access to the inter nal registers, the connection and the data memories. the connection memory locations can be read or written via the 16 bit microprocessor po rt. on the other hand, the data memory locations can only be read (but not written) from the microprocessor port. for the connecti on memory write ope ration, d0 to 11 of the data bus will be used and d12 to 15 are ignored (d12 to 15 should be driven low). for the connection memory read op eration, d0 to d11 will be used and d12 to d15 will output zeros. for the data memory read operation, d0 to d7 will be used and d8 to d15 will output zeros. see table on page 68 for the address mapping of the data memory. refer to figure 48 on page 82 for the microprocessor port timing. 2.9 digital phase-locked loop (dpll) operation the dpll meets the requirements of te lcordia gr-1244-core stratum 4 enhanced specifications (stratum 4e). it can be set into one of three operatin g modes: master, freerun or bypass. the input streams sti0-15 are always sa mpled with the st-bus input clock cki . the st-bus input frame pulse fpi denotes the input frame boundary. the objective of th e dpll is to generate the high speed internal clock mcktdm (see figure 25 on page 35). mcktdm provides timi ng for the tdm switching function and timing for the st-bus outputs. (in this context cko0-2 , fpo0-2 , sto0-15 and stohz0-15 are collectively known as the st-bus outputs.) ? in master mode, the dpll synchronizes to one of the ti ming reference inputs to generate the internal clock mcktdm. typically the timing references are from the network. the dpll provides functions such as automatic bit-error-free reference switching, jitte r attenuation and holdover. the master mode st-bus output clocks and frame pulses are synchronized to t he network reference and can be used as a system?s st-bus timing source. ? in freerun mode, the dpll is not synchronized to any of the timing references. it synthesizes the internal clock mcktdm based on the oscillator clock. typicall y freerun mode is used when a system?s timing is independent of the network. in that case, the freeru n mode st-bus output clocks and frame pulses must be used as the system?s st-bus timing source. ? in bypass mode, the dpll is completely bypassed. the analog phase-locked loop (apll) synchronizes to the st-bus input clock cki to generate the internal clock mcktdm. bypass mode is used when the system?s st-bus timing is supplied by another device, e.g. another zl50010 in master mode. table 14 shows the three operating modes of the dpll. the dpll is controlled by the dom (dpll operation mode) register and bit 14 of the cont rol register (cr). the dpll?s status is reported in the dpll house keeping register (dhkr). the dpoa (dpll output adjustment) register advances or delay s the st-bus outputs with respect to the reference. these r egisters are described in table 17 on pa ge 50 for cr, table 22 on page 55 for dom, table 23 on page 57 for doa, and table 24 on page 57 for dhkr. stin#qen3 action 1 replace lsb of every channel in quadrant 3 with "1" 0 no bit replacement occurs in quadrant 3 table 13 - quadrant frame 3 lsb replacement
zl50010 data sheet 32 zarlink semiconductor inc. table 14 - dpll operating mode settings the dpll intrinsic jitte r is 6.25 ns peak to peak. in master and freerun modes, t he dpll intrinsic jitter will be added onto the st-bus outputs. in bypass mode, the dpll is completely bypassed and the dpll intrinsic jitter will not be added to the st-bus outputs. 2.9.1 dpll master mode dpll master mode is selected by the setti ng shown in table 14. asserting the reset pin low will also put the dpll into master mode since reset clears all the registers. in master mode, the dpll generates the mcktdm clock synchronized to one of 3 timing reference signals. it provides jitter attenuation and holdover functions, and automatic reference switching between two of the timi ng references. mcktdm provides timing for the tdm switching function and for the st-bus outputs. hence the master mode st-bus output clocks and frame pulses are synchronized to the reference and can be used to provide a system?s st-bus timing. 2.9.1.1 master mode reference inputs the dpll has access to two independent external refere nces at the pri_ref and sec_ref input pins. typically pri_ref and sec_ref are from the network. additionally an internal 8 khz signal (cki /fpi) derived from the cki and fpi inputs can be selected to replace pri_ref. the reference chosen from between pri_ref and cki/fpi is called the primary reference. sec_ref is known as t he secondary reference. the p_refsel bit of the dom register is used to select between pri_re f and cki/fpi as the primary reference. either the primary reference (sel ected from between pri_ref and cki/ fpi) or the secondary reference (sec_ref) can be designated as the "preferred" reference via the refsel bit of the dom register. the remaining reference becomes the "backup" reference. for example, if sec_ref is the preferre d reference, then the backup reference is the primary reference selected from between pri_ref and cki/fpi. the preferred and backup references are used in automatic reference switching. the pri_ref and sec_ref inputs do not have to be at the same nominal frequency. each can be independently programmed to be either 8 khz, 1.544 mhz or 2.408 mhz via the fp1-0 and fs1-0 bits of the dom register. when the internal 8 khz signal cki/ fpi is selected as the primary reference in stead of pri_ref, the fp1-0 bits must be set to 00. the dpll operates on the rising edge of the selected reference. the polar ity of the pri_ref and sec_ref inputs can be inverted via the pinv and sinv bits of the dom register. bit 14 of cr bit 0 of dom mode 0 0 master mode 0 1 freerun mode 1 1 or 0 bypass mode
zl50010 data sheet 33 zarlink semiconductor inc. 2.9.1.2 master mode reference switching the dpll monitors both the primary and secondary reference. when the refere nce the dpll is currently synchronized to becomes invalid, the dpll?s response depends on which one of the failure detect modes has been chosen: autodetect, forced primary or forced secondary. one of these failure detect modes must be chosen via the fdm1-0 bits of the dom register . after a device reset via the reset pin, the autodetect mode is selected. in autodetect mode (automatic reference switching), if both references are va lid, the dpll will synchronize to the preferred reference. if the preferred reference becomes unreliable, the dpll c ontinues driving its output clock in a stable holdover state until it makes a switch to the back up reference. if the preferred reference recovers, the dpll makes a switch back to the preferred reference. if nece ssary, the switch back can be prevented by changing the preferred reference using the refsel bit in the dom register after the switch to the backup reference has occurred. if both references are unreliable, the dpll will drive it s output clock using stable holdover values until one of the references becomes valid. if cki/fpi is selected as the pr eferred reference, the user must ensure that the fpi and cki input signals are re-applied after the cki/fpi reference is lost (or failed). when the cki/fpi reference is lost, since fpi and cki are used to sample the input data streams sti0-15, the tdm switching from sti to sto will not work. in forced primary mode, the dpll will synchronize to the primary reference only. the dpll will not switch to the secondary reference under any circumstance including the loss of the primary reference. if the primary reference failed, the dpll will not go into holdover mode and sync hronization will be lost. simila rly in forced secondary mode the dpll will synchronize to the secondary reference only and will not switch to the primary reference or go into holdover under any circumstance. the choice of prefer red reference has no effect in these forced modes. when a conventional pll is locked to its reference, ther e is no phase difference between the input reference and the pll output. for the dpll, the input references can have any phase relationship between them. during a reference switch, if the dpll output follows the phase of the new reference, a large phase jump could occur. the phase jump would be transferred to the st -bus outputs. the dpll?s mtie (max imum time interval error) feature preserves the continuity of the dpll output so that it appears no reference sw itch had occurred. the mtie circuit is not perfect however, and a small time interval error is still incurred per reference switch. to align the dpll output clock to the nearest edge of the selected input reference, the mtie reset bit (mrst bit in the dom register) can be used. unlike some designs, switching between references whic h are at different nominal frequencies do not require intervention such as device reset. 2.9.1.3 dpll status reporting reference switching is managed by the state machine s hown in figure 27 on page 37. the state machine can be in one of six states corresponding to the names and numbe rs in the bubbles in figur e 27. the state number is reported in the st2-0 bits of the dhkr register. the validity of the pr imary and secondary references are reported in the pfd and sfd bits of t he dhkr register respectively. 2.9.1.4 master mode output offset adjustment the st-bus outputs (cko0-2 , fpo0-2 , sto0-15 and stohz0-15) can be shifted to lead (advancement) or lag (delay) the reference. the dpoa register provides this adjustment. coarse lead or lag adjustment is programmed via the pos6-0 bits, while fine delay (lag) control is via the skc2-0 bits.
zl50010 data sheet 34 zarlink semiconductor inc. 2.9.2 dpll freerun mode dpll freerun mode is selected by the setting in table 14. in freerun mode, the dpll is not synchronized to any of the reference inputs. the dpll synthesizes the internal clock mcktdm very accurately. mcktdm provides timing for the tdm switching function and for the st-bus output s. since the dpll is not synchronized to any of the reference inputs, the st-bus outputs are also not synchronized to any of the reference inputs. the dpll can switch to the freerun mode at any time. freerun mode is typically used when a master clock source is required, or immediately following system power-up before netwo rk synchronization is achieved. if a zl50010 is to be operated exclusively in freerun mode, then its st-bus output clock and frame pulse must be used as the st-bus input clock and frame pulse to a ll tdm devices in the system, including the device itself. 2.9.3 dpll bypass mode dpll bypass mode is selected by setting high bit 14 of t he control register (cr), as shown in table 14. the dpll is completely bypassed and the apll takes its input from cki instead of the oscillator. the apll multiplies the st- bus input clock cki with an appropria te frequency multiplication factor to generate the internal clock mcktdm. mcktdm is synchronized to cki. mcktdm provides timing for the tdm switching function and for the st-bus outputs. hence the st-bus outputs ar e synchronized to cki. the dpll intrin sic jitter will not be added onto the st- bus outputs because the dpll is completely bypassed. in this mode, the apll takes its input from cki instead of the os cillator. if the device is to be used in this mode only, the oscillator clock is not re quired and the external crystal os cillator or clock oscillator can be omitted. if the crystal oscillator or clock oscillator is omitted, the xtali pin mu st be held low and the xtalo pin must be left unconnected. bypass mode is used when another device, such as anot her zl50010 in master mode, is providing system timing.
zl50010 data sheet 35 zarlink semiconductor inc. 2.10 dpll fu nctional de scription figure 25 shows the functional block di agram of the dpll. major functional bl ocks are described in the following sections. when the dpll is in master or freerun m ode, the apll input is c20i from the o scillator and the apll multiplies c20i to generate the dpll master clock mckdpll. figure 25 - dpll functional block diagram 2.10.1 cki/fpi synchronizer and pri_ref select mux circuits the st-bus input frame pulse (fpi ) is sampled with the st-bus input clock (cki ) inside the cki/fpi synchronizer to create the 8 khz reference cki/fpi. either cki/fp i or pri_ref is selected by the reference select bit (p_refsel in the dom register) as the pri_ref_in t input to the reference select mux in figure 25. pll mtie pri_ref sec_ref state machine ref_selx forced_pri forced_sec mtie_reset reset pin phase_offset skew_control mcktdm frame skew freerun reference reference monitor reference monitor autodetect select mux freq_mod_pri freq_mod_sec frequency mode mux holdover mtie_start freq_mod ref_select ref_in ref_vir feedback los_pri los_sec (fig 27) (fig. 25) control fail_sec fail_pri ref (refsel bit in dom) (mrst bit in dom) (selected by fp0-1 bits in dom) (selected by fs0-1 bits in dom) (skc0-2 bits in dpoa) apll mckdpll c20i (pos0-6 bits in dpoa) (freerun bit in dom) (fig. 26) pri_ref select mux cki/fpi synchronizer cki fpi los control pri_ref_int p_refsel (p_refsel bit in dom) ref_sel
zl50010 data sheet 36 zarlink semiconductor inc. 2.10.2 reference select and frequency mode mux circuits the dpll accepts two simultaneous reference inputs and operates on their rising e dges. the state machine output ref_select chooses either the primary reference (pri_r ef_int signal) or the secondary reference (sec_ref signal) as the ref input to the skew control circ uit. ref_select also selects the frequency mode input (freq_mod) to the pll block from either freq_mod_p ri or freq_mod_sec. these are two bit wide signals from the dom register: freq_mod_pri corresponds to the fp1-0 bits, freq_mod_sec corresponds to the fps1-0 bits. 2.10.3 skew control circuit the skew control circuit delays the selected reference i nput with an 8 tap tapped delay line (see figure 26). the nominal delay between taps is 1.9 ns. thus the selected re ference can be delayed by 0 to 13.3 ns in steps of 1.9 ns (0 to 7 steps). the output tap is selected by skew_con trol which corresponds to the skc2-0 bits of the dpll output adjustment (dpoa) register. skewing the refer ence will cause the feedback signal in the pll block (feedback in figure 28 on page 38) to be delayed by the skew amount with respect to the original reference. this will cause the dpll output to be delayed by the skew amount. hence the st-bus outputs will be delayed by the skew amount. figure 26 - skew control circuit diagram 2.10.4 reference monitor circuit there are two identical reference monitor circuits, one for the primary reference pri_ref_int and one for the secondary reference sec_ref. each circuit continuously monitors its reference and reports the reference?s validity. the output signals are fail_p ri and fail_sec for the primary an d secondary monitors respectively. a logic high on either signal i ndicates that the corresponding reference has become invalid. the validity criteria depends on the frequency programmed for the reference. a re ference must meet all criteria applicable to its frequency, which are: ? the "minimum 90 ns" check is performed regardless of the programmed frequency. both the logic high and low duration of the reference must be at least 90 ns. ? the "period in specified range" check is perform ed regardless of the programmed frequency. each period must be within a range. for 1.544 mhz and 2.048 mhz, the range is 1-1/4 to 1+1/4 nominal period. for 8 khz, the range is 1-1/32 to 1+1/32 nominal period. ? if the programmed frequency is 1.544 mhz or 2.048 mhz, the "64 periods in specified range" check will be performed. the time taken for 64 consecutive cycles must be between 62 and 66 periods of the programmed frequency. the fail_pri and fail_sec signals are available at the dhkr regi ster pfd and sfd bits respectively. they are not affected by the choice of the preferred reference or failure detect mode and will alwa ys report the validity of the primary and secondary references respectively. mux reference skew_control delayed reference input
zl50010 data sheet 37 zarlink semiconductor inc. 2.10.5 los control circuit los control uses the results from the reference monitors to influence the transition of the state machine. the outputs of los control are affected by the choice of the failure detect mode (one of autodetect, forced primary, and forced secondary modes chosen via the dom regi ster fdm1-0 bits) as shown in table 15. table 15 - los outputs in the failure detect modes 2.10.6 state machine circuit the state machine manages the reference rearrangement pr ocess. the state machine can be in one of the six states shown as bubbles in figure 27. each bubble shows the state name and state number. depending on the 3 bit los control output {los_pri, los_sec, ref_sel} s hown in table 15, the state machine selects either pri_ref_int or sec_ref as the current reference. in autodetect mode, the state machine transitions between the states during reference rearrangem ent and switches the pll circuit bet ween normal and holdover operations. when the dpll goes from holdover to normal operation, the state machine goes through the mtie pri or mtie sec state to activate the mtie circuit. the mtie circuit prevents any significant phase shift at the pll output clock during the reference switch. note that the pll is still out putting holdover clock during the mtie pri or mtie sec state. in forced primary mode, the state mach ine will always stay in "normal pri" a nd never transition to "holdover pri". in forced secondary mode, the state machine will always st ay in "normal sec" and neve r transition to "holdover sec". the dhkr register st2-0 bits report the state number. in autodetect m ode, the st2-0 bits will follow the state transitions. in forced primary mode, st2-0 is always 0. in forced secondary mode, st2-0 is always 4. figure 27 - state machine diagram failure detect mode los_pri los_sec ref_sel autodetect fail_pri (from primary reference monitor) fail_sec (from secondary reference monitor) ref_selx (refsel bit in dom) (0: primary is preferred reference) (1: secondary is preferred reference) forced primary 0 1 0 forced secondary 1 0 1 holdover pri holdover sec mtie sec normal pri normal sec xxx = {los_pri, los_sec, ref_sel} 1xx or x01 0x0 or 011 0x0 100 1x0 or x01 or 100 or x01 0x0 or x1x 100 or x01 0x0 or 011 reset pin = 0 mtie pri 0x0 or x11 or x01 0 3 2 7 4 6 011
zl50010 data sheet 38 zarlink semiconductor inc. 2.10.7 maximum time interval error (mtie) circuit the mtie circuit prevents any significant change in the dpll output clock phase during a reference switch. the input references can have any relationship between t heir phases. the dpll output follows the selected input reference. thus a switch from one reference to another could cause a large phase jump in the dpll output if the mtie circuit did not exist. the phase jump would be trans ferred to the st-bus outputs. the mtie circuit works to preserve the continuity of the dpll output so that it appears no reference switch had occurred. the mtie circuit receives the skewed reference from the skew control circuit and delays it. this delayed signal is used as a virtual reference (ref_vir in figure 25 on page 35) to input to the pll block. therefore the virtual reference is a delayed version of the selected reference. during a reference switch, the state machine first changes the operation of the pll from normal to holdover. in holdover, the pll no longer uses the virtual reference signal, but generates a stable output clock us ing stored values. when the state machine changes to mtie pri or mtie sec, the pll block remains operating in holdover. the mt ie circuit measures the phase delay between the current phase (feedback signal in figure 25 on page 35) and th e phase of the new reference signal (ref_in in figure 25). the mtie circuit stores the measured delay. from now on the mtie circuit always delays the reference signal by the stored value to become the virtual reference. the virtual reference is now at the same phase position it would have been if the reference switch had not taken place. the state machine t hen returns the pll to normal operation. the pll now uses the new virtual reference signal. sinc e no phase step took place at the input of the pll, no phase step occurs at the pll output. in other words, refe rence switching will not cause a phase change at the pll block input, or at the pll output. during the measurement process, the new reference is sa mpled asynchronously with an internal clock. thus the delay between the new reference and the old virtual refe rence has a small measurement error. this measurement error will cause a small phase change (time interval error) at the pll output. even if there is no phase difference between the primary and secondary references, each time a reference switch is made the delay (phase offset) between the dpll input and output will change. the value of the delay is t he sum of the measurement errors from all the reference switches. after many switches, the delay between the selected input reference and the dpll output can become unacceptably large. the user should prov ide mtie reset (via mrst bit in the dom register) to realign the output clock to the nearest edge of the selected input reference. after the realignment, the phase offset between the input reference and dpll output is the am ount programmed into the dpoa register pos6-0 and skc2-0 bits. 2.10.8 phase-locked loop (pll) circuit as shown in figure 28, the pll circuit consists of a phase detector, phase offset adder, phase slope limiter, loop filter, digitally contro lled oscillator, divider and frequency select mux. figure 28 - block diagram of the pll module loop filter dco divider ref phase detector phase_offset phase freq_mod adder offset frequency mcktdm feedback phase slope limiter mux select frame c2m c1m5 holdover freerun
zl50010 data sheet 39 zarlink semiconductor inc. phase detector - the phase detector compares the virtual reference signal from the mtie circuit (ref_vir) with the feedback signal from the frequency select mux. it provides an error signal corresponding to the phase difference between the signals? rising edges. this error signal is passed to the phase offset adder. phase offset adder - the phase offset adder adds the phase_offset word (pos6-0 bits of the dpoa register) to the error signal from the phase dete ctor to create the final phase error. th is value is passed to the phase slope limiter. the phase offset word (pos6-0) can be positive or nega tive. since the p ll will stabilize to a situation where the average phase offset adder output is zero, a no n-zero phase offset word w ill result in a static phase offset between the input and output of the dpll. the phase offset word is a 7-bit 2?s complement value. if the selected input reference is 8 khz or 2.048 mhz, the step size of the static phase offset is 15.2 ns. the static phase offset can be set between -0.96 s and +0.97 s. if the selected input reference is 1.544 mhz, the step size is 20.2 ns and the static phase offset can be set between - 1.27 s and +1.29 s. the resolution of the skew control circuit is 1.9 ns. its ef fect is additional to that of the phase offset word. thus using the skew control bits (skc2-0 of the dpoa register) toge ther with the phase offset word, users can set a total static phase offset between -0.96 s and +0.99 s if the selected input referenc e is either 8 khz or 2.048 mhz. if the selected reference is 1.544 mhz, the total static phase offset can be between -1.27 s and +1.30 s. phase slope limiter - the phase slope limiter receives the error signal from the phase offset adder and ensures that the dpll output responds to all in put transient conditions with an output phase slope below a preset limit. the limit is based upon telecom standards requirements. loop filter - the loop filter is similar to a first order low pass filter with a 1.52 hz cutoff frequency for all 3 reference frequency selections (8 khz, 1.544 mhz or 2.048 mhz). this filter defines the jitter transfer characteristic of the dpll. digitally controlled oscillator (dco) - the dco generates a high speed digital clock output. the dco?s frequency is modulated by the frequency offset value from the loop filter. the dco output is the mcktdm clock in figure 25 on page 35 and figure 28 on page 38. mcktdm pr ovides timing for the tdm switching function, and timing for the st-bus outputs. when the state machine is in the normal state, the dco accepts the offset frequency value which represents the limited and filtered phase error between the input re ference and the dco feedback signal. based on the offset value the dco generates an output clock which is synchronized to the selected input reference. when the state machine is in the ho ldover state, the dco uses a frequenc y offset value which has been stored 32 ms to 64 ms prior to exiting from the normal state. thus the dco is running at the same frequency it was previously running at when the state machine was in the normal state. when the dpll is in freerun mode, the frequency offset is ignored and the dco is free running at its preset center frequency. divider - the divider divides down the dco output frequency. the following signals are generated: ? c2m (a 2.048 mhz clock) ? c1m5 (a 1.544 mhz clock) ? frame (an 8 khz frame pulse) one of these signals is selected as the pll feedback refe rence signal by the frequen cy select mux circuit. the clocks have 50% nominal duty cycle. frame is a 122 ns wi de negative frame pulse. th e duty cycle of the clocks are not affected by the crystal oscillator duty cycle. since these signals are generat ed from a common signal inside the dpll, the frame pulse and clock outputs are always locked to one another. they are also locked to the selected input reference when the dpll is in lock. frequency select mux - according to the selected input reference of the dpll, this multiplexer w ill select the appropriate divider output c2m, c1m5 or frame as the feedback signal to the pll and mtie circuits.
zl50010 data sheet 40 zarlink semiconductor inc. 2.11 dpll performance the following are some synchronizer performance indicato rs and their definitions. the performance of the dpll is also indicated. 2.11.1 intrinsic jitter intrinsic jitter is the jitter produced by a synchronizer and is measured at its output. it is measured by applying a jitter free reference signal to the input of the device, an d measuring its output jitter. intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. intrinsic jitter is usuall y measured with various band-li miting filters depending on the applicable standards. intrinsic jitter is applicable only in master and freerun modes since in bypass mode the dpll is completely bypassed. the dpll?s intrinsic jitter is 6.25 ns peak to peak. the intrinsi c jitter will be added to the st-bus outputs cko0-2 , fpo0-2 , sto0-15 and stohz0-15. since the dpll master cl ock (mckdpll) comes from the on chip apll which is driven by the oscillator , any jitter on the oscillato r will be added unattenuated on to the intrinsic jitter. 2.11.2 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly without cycle slips (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. the applied jitter magnitude and the ji tter frequency depends on the applicable standards. the dpll?s jitter tolerance meets telcordia gr-1244-cor e ds1 reference input jitter tolerance requirements. 2.11.3 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. since intrinsic jitter is always present, jitter attenuation will appear to be lowe r for small input jitter signals than for large ones. consequently, accurate jitter transfer functi on measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). the dpll?s jitter transfer characteristic is determined by the internal 1.52 hz low pass loop filter and the phase slope limiter. the dpll is a second order, type 2 pll. figure 29 on page 41 shows the dpll jitter transfer characteristic over a wide range of frequencies, while figure 30 on page 41 expands the portion of figure 29 around the 0 db jitter transfer region. the jitter transfer f unction can be described as a low pass filter to 1.52 hz, - 20 db/decade, with peaking less then 0.5 db. 2.11.4 frequency accuracy frequency accuracy is defined as the absolute tolerance of an output clock when the synchronizer is not locked to an external reference, but is in a free running mode. in freerun mode, the dpll is not synchronized to any re ference. the dpll provides output clocks and frame pulses based on the dpll master clock. the pll block? s dco circuit ignores its frequency offset input and free runs at its center frequency. because of the granularity of the center fr equency control value, the dco free run frequency is -0.03 ppm off the ideal frequency. the dco is clocked by the dpll master clock mckdpll. the apll generates the dpll master clock from the oscillator . thus the dpll free run accuracy is affected by the oscillator accuracy. the dpll free run accuracy is -0.03 ppm plus the accuracy of the oscillator.
zl50010 data sheet 41 zarlink semiconductor inc. figure 29 - dpll jitter transfer function diagram - wide range of frequencies figure 30 - detailed dpll jitter transfer function diagram (wander transfer diagram)
zl50010 data sheet 42 zarlink semiconductor inc. 2.11.5 holdover accuracy holdover accuracy is defined as the absolute tolerance of an output clock signal, when the synchronizer is not locked to an external reference signal but is operating using storage techniques. in the holdover state, the dpll is not locked to any reference. the dpll generates its output clock mcktdm using values which were stored while the dpll was locked to the selected reference in the normal state. the values were stored 32 ms to 64 ms prio r to exiting from the normal state. two factors affect the holdover accuracy: large jitter on the reference prior to the state change, and the oscillator frequency drift since the state change. note that it is th e change in the oscillator frequency between the normal and holdover states which affect holdover accuracy, not the absolute frequency of the oscillator. the dpll master clock is derived from the oscillator. when the dpll is in lock, the dpll output frequency is exactly the same as th at of the input refe rence. the dpll will compensate for any changes in the absolute frequency of the oscillator. in holdover, the dpll output frequency is generated using values stored while the dpll was in lock. thus the dpll can no longer compensate for changes in the oscillator frequency. the holdover frequency will change if the oscillator frequency has deviated since the dpll was in lock. when there was no jitter in the reference, and there is no change in the oscillator frequency, the dpll holdover accuracy is within +/-0.07 ppm, which translates into maximum 49 frame slips (6.125 ms) in 24 hours. any change in the osci llator frequency since the transition out of the normal state will change the holdover frequency. for example, a +/-32 ppm oscillator ma y have a temperature coefficient of +/-0.1 ppm/ c. thus a 10 c change since the dpll was last in the normal state will change the holdover frequency by an additional +/-1 ppm, which is much greater than t he +/-0.07 ppm of the dpll. 2.11.6 locking range the locking range is the input frequency range over which the dpll must be able to pull into synchronization and to maintain the synchronization. the locking range is defined by the loop filter circuit and is equal to +/- 298 ppm. note that the locking range is related to the oscillator frequency. if the os cillator frequency is -100 ppm, the whole locking range also shifts by -100 ppm downwards to become -398 ppm to +198 ppm. 2.11.7 phase slope the phase slope, or phase alignment speed, is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typicall y the output signal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final i nput signal. many telecom standards state that the phase slope may not exceed a certain value, usually 81 ns/1.327 ms (61 ppm). this can be achieved by limiting the phase detector output to 61 ppm or less. for the dpll, the phase slope limiter circuit lim its the maximum phase slope to 56 ppm or 7 ns/125 s. the phase slope limit meets telcordia gr-1244-core requirements. 2.11.8 mtie mtie (maximum time interval error) is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. for the dpll, mtie is less than 21 ns per reference switch.
zl50010 data sheet 43 zarlink semiconductor inc. 2.11.9 phase lock time the phase lock time is the time it takes a synchronizer to phase lock to the input signal. phase lock occurs when the input and the output sig nals are not changing in phase with respect to each other (not including jitter). lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) pll loop filter iv) pll limiter although a short phase lock time is des irable, it is not always achievable due to other synchronizer requirements. for instance, better jitter transfer pe rformance is obtained with a lower fr equency loop filter which increases lock time; and better (smaller) phase slope performance (limiter) will increase lock time. the dpll loop filter and limiter have been optimized to meet the telcordia gr-1244- core jitter transfer and phase alignment speed requirements. if the frequency of the dpll internal feedback signal is -50 ppm and the frequency of the input reference is +50 ppm, then the phase lock time is typically 15 seconds. however, in a device power up situation, phase lock time can be up to 50 se conds. the phase lock time meets telcordia gr-1244-core stratum 4e requirements. 2.12 alignment between input and output frame pulses when the device is in dpll master mode, and cki/fpi is the selected input reference and has no jitter, then the st-bus output frame pulses align very closely to the st-bus input fram e pulse. see figure 40 on page 75 for details. (the alignment shown is for when all bits in the dp oa register are 0.) if the ck i/fpi reference has jitter, the output frame pulses will still align to the input frame pul se but the offset value is a function of the input jitter. when the device is in dpll master mode, and the selected input reference is not cki/fpi, then the output frame pulses have no relationship with respect to the input frame pulse. in this case, the device?s output frame pulse(s) must be used as the frame pulse(s) for the system, which me ans that the output frame pu lse(s) will be supplied as the input frame pulse to all devi ces, including the device itself. when the device is in dpll bypass mode, the output fr ame pulses align closely to the input frame pulse. see figure 40 for details.
zl50010 data sheet 44 zarlink semiconductor inc. 3.0 oscillator requirements in dpll master and freerun modes, the apll module requ ires a 20 mhz clock source at the xtali pin. the 20 mhz clock can be generated by connecting an external crystal oscillator to the xtali and xtalo pins, or by connecting an external clock os cillator to the xtali pin. if the device is to be used in dpll bypass mode only, t he 20 mhz clock is not requir ed and the crystal oscillator or clock oscillator can be omitted. if the crystal oscillator or cl ock oscillator is omitted, the xtali pin must be held low and the xtalo pin must be left unconnected. 3.1 external crystal oscillator a complete external crystal oscillator circuit made up of a crystal, resistor and capacitors is shown in figure 31. figure 31 - crystal oscillator circuit the accuracy of a crystal o scillator circuit depends on th e crystal tolerance as well as the load capacitance tolerance. typically, for a 20 mhz crystal specified wi th a 32 pf load capacitance, each 1 pf change in load capacitance contributes approximately 9ppm to the fr equency deviation. consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. the trimmer capacitor may be used to compensate for capacitive effects. if accuracy is not a concern, then the trimmer may be removed, the 39 pf capacitor may be increased to 56 pf, and a wider tolerance crystal may be substituted. the crystal should be a fundamental mode type - not an over tone. the fundamental mode crystal permits a simpler oscillator circuit with no additional fi lter components and is less likely to generate spurious responses. the crystal accuracy only affects the output clock accuracy in th e freerun mode. the crystal specification is as follows. frequency: 20 mhz tolerance: as required oscillation mode: fundamental resonance mode: parallel load capacitance: 32 pf maximum series resistance: 35 ? approximate drive level: 1 mw e.g., r1b23b32-20.0 mhz (20 ppm absolute, 6 ppm 0c to 50c, 32 pf, 25 ? ) xtalo 56 pf 1m ? 39 pf 3-50 pf 20 mhz zl50010 xtali 100 ? 1uh 1 uh inductor: may improve stability and is optional
zl50010 data sheet 45 zarlink semiconductor inc. 3.2 external clock oscillator when an external clock oscillator is used, numerous pa rameters must be considered. this includes absolute frequency, frequency change over temperature, output ri se and fall times, output levels and duty cycle. for applications requiring 32 ppm clock accuracy, the following cl ock oscillator module may be used: fox f7c-2e3-20.0 mhz frequency: 20 mhz tolerance: 25 ppm 0c to 70c rise & fall time: 10 ns (0.33v 2.97v 15 pf) duty cycle: 40% to 60% the output clock should be connected directly (not ac coupled) to the xtali input of the device, and the xtalo output should be left open as shown in figure 32. figure 32 - external clock oscillator circuit +3.3 v 20 mhz out gnd 0.1 uf +3.3 v xtalo xtali no connection zl50010
zl50010 data sheet 46 zarlink semiconductor inc. 4.0 device reset and initialization the reset pin is used to reset the device. when the pin is low, it synchronously puts the device into its reset state. it disables the sto0 - 15 outputs, drives the stohz 0 - 15 outputs to high, clears the device registers and the internal counters. upon power up, the device should be initialized as follows: ? set ode pin to low to disable the sto0-15 output and to drive the stohz 0-15 to high. ? set the trst pin to low to disable the jtag tap controller. ? reset the device by pulsing the reset pin to low for longer than 1 ms. ? after releasing the reset pin from low to high, wait for 600 s for the apll module and the crystal oscillator to be stabilized before starti ng the first microprocessor port access cycle. ? program the register to define the frequency of the cki input. ? wait for 600 s for the apll module to be stabilized before starting the next microprocessor port access cycle. ? configure the dpll. after a device reset, the dpll def aults are: master mode, failure detect mode is autodetect, primary reference is pri_ref at 8 khz, sec_ref frequency is 8 khz, preferred reference is the primary reference, polarities of pri_ref and sec_ref are not inverted. ? if dpll master mode is selected, wait 50 seconds for the dpll to synchronize to the reference. ? use the memory block programming mode to initialize the connection memory. ? release the ode pin to high after the connection memory is programmed such that bus contention will not occur at the serial stream outputs sto0-15. 5.0 jtag support the zl50010 jtag interface conforms to the boundar y-scan ieee1149.1 standard. the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. 5.1 test access port (tap) the test access port (tap) accesses the zl50010 test func tions. it consists of 3 i nput pins and 1 output pin as follows: ? test clock input (tck) - tck provides the clock for the test logi c. the tck does not interfere with any on- chip clock and thus remains independent in the functional mode. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently wi th the operation of the device and without interfering with the on-chip logic. ? test mode select input (tms) - the tap controller uses the logic signals received at the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to vdd when it is not driven from an external source. ? test data input (tdi) - serial input data applied to this port is fed ei ther into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to vdd when it is not driven from an external source. ? test data output (tdo) - depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are se rially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst) - resets the jtag scan structure. this pin is internally pulled to vdd when it is not driven from an external source.
zl50010 data sheet 47 zarlink semiconductor inc. 5.2 instruction register the zl50010 uses the public instructions defined in the ie ee 1149.1 standard. the jtag interface contains a four- bit instruction register. inst ructions are serially loaded into the instru ction register from the tdi when the tap controller is in its shifted-ir state. these instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the in struction is current and to define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. 5.3 test data register as specified in ieee 11 49.1, the zl50010 jtag interface cont ains three test data registers: ? the boundary-scan register - the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the zl50010 core logic. ? the bypass register - the bypass register is a single stage shift register that provides a one-bit path from tdi to its tdo. ? the device identification register - the jtag device id for the zl50010 is 0c35a14b h . version<31:28>: 0000 part no. <27:12>: 1100 0011 0101 1010 manufacturer id<11:1>: 0001 0100 101 lsb<0>: 1 5.4 bsdl a bsdl (boundary scan description language) file is available from zarlink semiconductor to aid in the use of the ieee 1149 test interface.
zl50010 data sheet 48 zarlink semiconductor inc. 6.0 register address mapping external address a11 - a0 cpu access register 000 h r/w control register, cr 001 h r/w internal mode selection, ims 010 h r/w ber start receive register, bsrr 011 h r/w ber length register, blr 012 h read only ber count register, bcr 030 h r/w dpll operation mode, dom 031 h r/w dpll output adjustment, dpoa 032 h read only dpll house keeping register, dhkr 100 h r/w stream0 input control register, sicr0 101 h r/w stream0 input delay register, sidr0 102 h r/w stream1 input control register, sicr1 103 h r/w stream1 input delay register, sidr1 104 h r/w stream2 input control register, sicr2 105 h r/w stream2 input delay register, sidr2 106 h r/w stream3 input control register, sicr3 107 h r/w stream3 input delay register, sidr3 108 h r/w stream4 input control register, sicr4 109 h r/w stream4 input delay register, sidr4 10a h r/w stream5 input control register, sicr5 10b h r/w stream5 input delay register, sidr5 10c h r/w stream6 input control register, sicr6 10d h r/w stream6 input delay register, sidr6 10e h r/w stream7 input control register, sicr7 10f h r/w stream7 input delay register, sidr7 110 h r/w stream8 input control register, sicr8 111 h r/w stream8 input delay register, sidr8 112 h r/w stream9 input control register, sicr9 113 h r/w stream9 input delay register, sidr9 114 h r/w stream10 input cont rol register, sicr10 115 h r/w stream10 input dela y register, sidr10 116 h r/w stream11 input control register, sicr11 117 h r/w stream11 input delay register, sidr11 118 h r/w stream12 input cont rol register, sicr12 119 h r/w stream12 input dela y register, sidr12 11a h r/w stream13 input cont rol register, sicr13 11b h r/w stream13 input dela y register, sidr13 11c h r/w stream14 input cont rol register, sicr14
zl50010 data sheet 49 zarlink semiconductor inc. table 16 - address map for device specific registers 11d h r/w stream14 input dela y register, sidr14 11e h r/w stream15 input cont rol register, sicr15 11f h r/w stream15 input dela y register, sidr15 200 h r/w stream0 output control register, socr0 201 h r/w stream0 output delay register, soor0 202 h r/w stream1 output control register, socr1 203 h r/w stream1 output delay register, soor1 204 h r/w stream2 output control register, socr2 205 h r/w stream2 output delay register, soor2 206 h r/w stream3 output control register, socr3 207 h r/w stream3 output delay register, soor3 208 h r/w stream4 output control register, socr4 209 h r/w stream4 output delay register, soor4 20a h r/w stream5 output control register, socr5 20b h r/w stream5 output delay register, soor5 20c h r/w stream6 output control register, socr6 20d h r/w stream6 output delay register, soor6 20e h r/w stream7 output control register, socr7 20f h r/w stream7 output delay register, soor7 210 h r/w stream8 output control register, socr8 211 h r/w stream8 output delay register, soor8 212 h r/w stream9 output control register, socr9 213 h r/w stream9 output delay register, soor9 214 h r/w stream10 output control register, socr10 215 h r/w stream10 output delay register, soor10 216 h r/w stream11 output control register, socr11 217 h r/w stream11 output delay register, soor11 218 h r/w stream12 output control register, socr12 219 h r/w stream12 output delay register, soor12 21a h r/w stream13 output control register, socr13 21b h r/w stream13 output delay register, soor13 21c h r/w stream14 output control register, socr14 21d h r/w stream14 output delay register, soor14 21e h r/w stream15 output control register, socr15 21f h r/w stream15 output delay register, soor15 external address a11 - a0 cpu access register
zl50010 data sheet 50 zarlink semiconductor inc. 7.0 detail register description bit name description 15 unused reserved. in normal functional mode, these bits must be set to zero. 14 slv dpll bypass mode enable. when this bit is zero, the dpll is in master or freerun mode. when th is bit is high, the dpll is in bypass mode. 13 fbden frame boundary determination disable. when this bit is low, the long term frame boundary determinat ion mode is disabled. when it is high, the det ermination mode is enabled. set this bit from low to high after waiting for 600 s upon device power up. 12 - 10 ckin2-0 input st bus clock (cki ) and frame pulse (fpi ) selection. 9 ckfp2 output st bus clock cko2 and frame pulse fpo2 selection. when this bit is low, cko2 is 32.768 mhz clock and fpo2 is 30 ns wide frame pulse when this bit is high, cko2 is 16.384 mhz clock and fpo2 is 61 ns wide frame pulse 8 ckfp1 output st bus clock cko1 and frame pulse fpo1 selection. when this bit is low, cko1 is 16.384 mhz clock and fpo1 is 61 ns wide frame pulse when this bit is high, cko1 is 8.192 mhz clock and fpo1 is 122 ns wide frame pulse 7 ckfp0 output st bus clock cko0 and frame pulse fpo0 selection. when this bit is low, cko0 is 4.096 mhz clock and fpo0 is 244 ns wide frame pulse when this bit is high, cko0 is 8.192 mhz clock and fpo0 is 122 ns wide frame pulse 6cber bit error rate counter clear: when this bit is high, it re sets the internal bit error counter and the content of th e bit error count r egister (bcr) to zero. upon completion of the reset, set this bit to zero. 5 sber bit error rate test start: when this bit is high, it enables the ber transmitter and receiver; starts the bit error rate test. the bit error test result is kept in the bit error count (bcr) register. upon the completion of the ber test, set this bit to zero. 4 mbpe memory block programming enable: when this bit is high, the connection memory block programming mode is enabled to program bit 0 to bit 2 of the connection memory. when it is low, the memory block programming mode is disabled. table 17 - control register (cr) bits external read/write address: 000 h reset value: 0000 h 151413121110 9 8 7 6 5 4 3210 0slvfbd en ckin 2 ckin 1 ckin 0 ckfp 2 ckfp 1 ckfp 0 cber sber mbpe osb ms2 ms1 ms0 ckin2 - 0 fpi low cycle cki 000 61 ns 16.384 mhz 001 122 ns 8.192 mhz 010 244 ns 4.096 mhz 011 - 111 reserved
zl50010 data sheet 51 zarlink semiconductor inc. 3osb output stand by bit: this bit enables the sto0 - 15 and the stohz 0 -15 serial outputs. the following table describes the hiz control of the serial data outputs: 2 - 0 ms2-0 memory select bit. these bits are used to select connection memory or data memory: bit name description table 17 - control register (cr) bits (continued) external read/write address: 000 h reset value: 0000 h 151413121110 9 8 7 6 5 4 3210 0slvfbd en ckin 2 ckin 1 ckin 0 ckfp 2 ckfp 1 ckfp 0 cber sber mbpe osb ms2 ms1 ms0 reset pin ode pin osb bit sto0-15 stohz 0-15 0 x x hiz driven high 1 0 x hiz driven high 1 1 0 hiz driven high 1 1 1 active active ms2 - 0 memory selection 000 connection memory read/write 001 data memory read 010 - 111 reserved
zl50010 data sheet 52 zarlink semiconductor inc. bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 ckinp st bus clock input (cki ) polarity when this bit is low, the cki falling edge aligns with the frame boundary. when this bit is high, the cki rising edge aligns with the frame boundary. 10 fpinp frame pulse input (fpi ) polarity when this bit is low, the input frame pulse fpi should have the negative frame pulse format. when this bit is hi gh, the input frame pulse fpi should have the positive frame pulse format. 9ck2p st bus clock output (cko2 ) polarity when this bit is low, the output clock cko2 falling edge aligns with the frame boundary. when this bit is high, the output clock cko2 rising edge aligns with the frame boundary. 8fp2p frame pulse output (fpo2 ) polarity when this bit is low, the output frame pulse fpo2 has the negative frame pulse format. when this bit is high, the output frame pulse fpo2 has the positive frame pulse format. 7ck1p st bus clock output (cko1 ) polarity when this bit is low, the output clock cko1 falling edge aligns with the frame bound- ary. when this bit is high, the output clock cko1 rising edge aligns with the frame boundary. 6fp1p frame pulse output (fpo1 ) polarity when this bit is low, the output frame pulse fpo1 has the negative frame pulse format. when this bit is high, the output frame pulse fpo1 has the positive frame pulse format. 5ck0p st bus clock output (cko0 ) polarity when this bit is low, the output clock cko0 falling edge aligns with the frame boundary. when this bit is high, the output clock cko0 rising edge aligns with the frame boundary. 4fp0p frame pulse output (fpo0 ) polarity when this bit is low, the output frame pulse fpo0 has the negative frame pulse format. when this bit is high, the output frame pulse fpo0 has the positive frame pulse format. 3 - 1 bpd2 - 0 block programming data: these bits refer to the value to be loaded into the connection memory. whenever the memory block programming feature is activated. after the mbpe bit in the control register is set to high and the mbps bit is set to high, the contents of the bits bpd0 to bpd2 are loaded into bit 0 to bit 2 of the connection memory. bit 3 to bit 11 of the connection memory are zeroed. table 18 - internal mode selection (ims) register bits external read/write address: 001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 ckinp fpinp ck2p fp2p ck1p fp1p ck0p fp0p bpd 2 bpd 1 bpd 0 mbps
zl50010 data sheet 53 zarlink semiconductor inc. table 19 - ber start receiving register (bsrr) bits 0 mbps memory block programming start: a zero to one transition of this bit starts the memory block programming func tion. the mbps, bpd0 to bpd 2 bits in this register must be defined in the same write operation. once the mbpe bit in the control register is set to high, the device requires 50 s to complete the block programming. after the programming function has finish ed, the mbps bit returns to low indicating the opera- tion is completed. when the mbps is hi gh, the mbps or mbpe can be set to low to abort the programming operation. to ensure proper block programming operation, when mbps is high the bpd0 to bpd2 bits in this regist er must not be changed. whenever the microprocessor writes a one to the mbps bit, the block programming function is started, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting. bit name description 15 - 13 8 - 7 unused reserved. in normal functional mode, these bits must be set to zero. 12 - 9 brsa3 - 0 ber receive stream address bits: the binary value of these bits refers to the input stream which receives the ber data. 6 - 0 brca6 - 0 ber receive channel address bits: the binary value of these bits refers to the input channel in which the ber data starts to be compared. bit name description table 18 - internal mode selection (ims) register bits (continued) external read/write address: 001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 ckinp fpinp ck2p fp2p ck1p fp1p ck0p fp0p bpd 2 bpd 1 bpd 0 mbps external read/write address: 010 h reset value: 0000 h 1514131211109876543210 000br sa3 br sa2 br sa1 br sa0 00br ca6 br ca5 br ca4 br ca3 br ca2 br ca1 br ca0
zl50010 data sheet 54 zarlink semiconductor inc. table 20 - ber length register (blr) bits table 21 - ber count register (bcr) bits bit name description 15 - 8 unused reserved. in normal functional mode, these bits must be set to zero. 7 - 0 bl7 - 0 ber length bits: the binary value of these bits re fers to the number of channels. the maximum numbers of ber channels are 32, 64 and 128 for the data rate of 2.048 mbps, 4.096 mbps and 8.192 mbps modes respectively. the minimum number of ber channel is 1. if these bits are set to zero, no ber test will be performed. bit name description 15 - 0 bc15 - 0 ber count bits: the binary value of these bits refers to the bit error counts. when it reaches its maximum value of hex ffff, the value will not be changed any more. external read/write address: 011 h reset value: 0000h 1514131211109876543210 0 0 0 0 0 0 0 0 bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 external read address: 012 h reset value: 0000h 1514131211109876543210 bc 15 bc 14 bc 13 bc 12 bc 11 bc 10 bc 9 bc 8 bc 7 bc 6 bc 5 bc 4 bc 3 bc 2 bc 1 bc 0
zl50010 data sheet 55 zarlink semiconductor inc. bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 mrst mtie reset bit: when mrst is low, the dpll mtie circuit is functional. when mrst is high, the mtie circuit will be reset - t he dpll output will align with the nearest edge of the selected reference. (note: after t he realignment, the phase offset between the input reference and dpll output is the am ount programmed into the dpoa register.) 10 - 9 fdm1 - 0 failure detect mode bits: these two bits are used to choose among one of three failure detection modes. 8sinv sec_ref input inversion: when this bit is low, the sec_ref input will not be inverted. when this bit is high, the sec_ref input will be inverted. 7pinv pri_ref input inversion: when this bit is low, the pri_ref input will not be inverted. when this bit is high, t he pri_ref input will be inverted. 6 - 5 fs1 - fs0 sec_ref frequency selection bits: these bits are used to specify the nominal clock frequency of the sec_ref input. table 22 - dpll operation mode (dom) register bits external read/write address: 030 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 mrst fdm1 fdm0 sinv pinv fs1 fs0 fp1 fp0 ref sel p_ref sel free run fdm1 fdm0 failure detection mode 00 autodetect - automatic reference re-arrangement based on reference monitor results and choice of preferred reference 01reserved 10 forced primary - the dpll is forced to use primary reference only 11 forced secondary - the dpll is forced to use secondary reference only fs1 fs0 secondary reference 00 8khz 01 1.544mhz 10 2.048mhz 11 reserved
zl50010 data sheet 56 zarlink semiconductor inc. 4 - 3 fp1 - fp0 pri_ref frequency selection bits: these bits are used to specify the nominal clock frequency of the pri_ref input . when the p_refsel bit is high to select th e internal 8 khz signal (derived from the fpi and cki inputs) as primary reference, these bits must be set to 00. 2 refsel preferred reference selection bit: when this bit is low, the preferred reference is the primary reference selected via the p_ref sel bit (pri_ref or internal 8 khz from fpi and cki ). when this bit is high, the prefer red reference is the secondary reference (sec_ref). 1 p_refsel primary reference source selection bit: this bit is used to select the primary reference input to the dpll from between 2 sources. when this bit is low, the primary reference is from the pri_ref pin. when this bit is high, the primary reference is from the internal 8 khz generated from the fpi and cki inputs. when this bit is high, the fp1-0 bits must be set to 00. if the internal 8 khz signal is selected as the primary reference, the user must ensure that the fpi and cki input signals will be re-applied after the internal 8 khz signal is lost (or failed). if fpi or cki is not presented to the devi ce, the device cannot accept sti0-15 input data. 0 freerun freerun control bit: when this bit is low and bit 14 of the control register is low, the dpll is in master mode. when this bit is hi gh and bit 14 of the control register is low, the dpll is in freerun mode. this bit has no effect when bit 14 of the control register is high. bit name description table 22 - dpll operation mode (dom) register bits (continued) external read/write address: 030 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 mrst fdm1 fdm0 sinv pinv fs1 fs0 fp1 fp0 ref sel p_ref sel free run fp1 fp0 primary reference 0 0 8 khz (pri_ref or cki/fpi) 01 1.544mhz 10 2.048mhz 1 1 reserved
zl50010 data sheet 57 zarlink semiconductor inc. table 23 - dpll output adjustment (dpoa) register bits table 24 - dpll house keeping (dhkr) register bits bit name description 15 - 10 unused reserved. in normal functional mode, these bits must be set to zero. 9 - 3 pos6 - 0 phase offset bits: these 7 bits form the 2?s complement phase offset word which controls the dpll output phase offset. the dpll output is advanced (leads the refer- ence) if the word is positive. the dpll outp ut is delayed (lags the reference) if the word is negative. the net effect is th at the st-bus outputs will be advanced or delayed by the programmed amount. the offset is in step of 15.2 ns if the input reference is 8 khz or 2.048 mhz. the offset is in step of 20.2 ns if the input referenc e is 1.544 mhz. these bits have no effect in freerun or bypass mode. 2 - 0 skc2 - 0 skew control bits: these 3 bits control the delay of the dpll outputs from 0 to 13.3 ns in steps of 1.9 ns. the net effect is that the st-bus outputs will be delayed by the programmed amount. these bits have no effect in freerun or bypass mode. bit name description 15 - 6 unused reserved. in normal functional mode, these bits must be set to zero. 5sfd secondary fail detecti on bit (read only bit): this bit reports the validity of the sec_ref signal. when the secondary reference fails, this bit is set to high. 4pfd primary fail detection bit (read only bit): this bit reports the validity of the primary reference signal selected by the p_ref sel bit in the dom register. when the selected primary reference fails, this bit is set to high. 3lmt dpll limit bit (read only bit): this bit indicates that the phase slope limiter is limiting the phase difference between the input reference and the feedback reference. 2 - 0 st2- 0 dpll state bits (read only bit): these bits report the state of the dpll state machine. the state numbers are shown in the bubbles in figure 27 on page 37. external read/write address: 031 h reset value: 0000 h 1514131211109876543210 000000 pos6 pos5 pos4 pos3 pos2 pos1 pos0 skc2 skc1 skc0 external read address: 032 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000sfdpfdlmtst2st1st0
zl50010 data sheet 58 zarlink semiconductor inc. bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8stin#qen3 quadrant frame 3 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch24 to 31, ch48 to 63 and ch96 to 127 for the 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively. 7stin#qen2 quadrant frame 2 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch16 to 23, ch32 to 47 and ch64 to 95 for the 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively. 6stin#qen1 quadrant frame 1 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch8 to 15, ch16 to 31 and ch32 to 63 for the 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively. 5stin#qen0 quadrant frame 0 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch0 to 7, ch0 to 15 and ch0 to 31 for 2.048 mbps, the 4.096 mbps and 8.192 mbps mode respectively. table 25 - stream input control register 0 to 7 (sicr0 to sicr7) external read/write address: 100 h , 102 h , 104 h , 106 h , 108 h , 10a h , 10c h , 10e h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sicr00000000stin0 qen3 stin0 qen2 stin0 qen1 stin0 qen0 stin0 smp1 stin0 smp0 stin0 dr2 stin0 dr1 stin0 dr0 sicr10000000stin1 qen3 stin1 qen2 stin1 qen1 stin1 qen0 stin1 smp1 stin1 smp0 stin1 dr2 stin1 dr1 stin1 dr0 sicr20000000stin2 qen3 stin2 qen2 stin2 qen1 stin2 qen0 stin2 smp1 stin2 smp0 stin2 dr2 stin2 dr1 stin2 dr0 sicr30000000stin3 qen3 stin3 qen2 stin3 qen1 stin3 qen0 stin3 smp1 stin3 smp0 stin3 dr2 stin3 dr1 stin3 dr0 sicr40000000stin4 qen3 stin4 qen2 stin4 qen1 stin4 qen0 stin4 smp1 stin4 smp0 stin4 dr2 stin4 dr1 stin4 dr0 sicr50000000stin5 qen3 stin5 qen2 stin5 qen1 stin5 qen0 stin5 smp1 stin5 smp0 stin5 dr2 stin5 dr1 stin5 dr0 sicr60000000stin6 qen3 stin6 qen2 stin6 qen1 stin6 qen0 stin6 smp1 stin6 smp0 stin6 dr2 stin6 dr1 stin6 dr0 sicr70000000stin7 qen3 stin7 qen2 stin7 qen1 stin7 qen0 stin7 smp1 stin7 smp0 stin7 dr2 stin7 dr1 stin7 dr0
zl50010 data sheet 59 zarlink semiconductor inc. 4 - 3 stin#smp1 - 0 input data sampling point selection bits : 2 - 0 stin#dr2 - 0 input data rate selection bits: note: # denotes input stream from 0 to 7 bit name description table 25 - stream input control register 0 to 7 (sicr0 to sicr7) (continued) external read/write address: 100 h , 102 h , 104 h , 106 h , 108 h , 10a h , 10c h , 10e h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sicr00000000stin0 qen3 stin0 qen2 stin0 qen1 stin0 qen0 stin0 smp1 stin0 smp0 stin0 dr2 stin0 dr1 stin0 dr0 sicr10000000stin1 qen3 stin1 qen2 stin1 qen1 stin1 qen0 stin1 smp1 stin1 smp0 stin1 dr2 stin1 dr1 stin1 dr0 sicr20000000stin2 qen3 stin2 qen2 stin2 qen1 stin2 qen0 stin2 smp1 stin2 smp0 stin2 dr2 stin2 dr1 stin2 dr0 sicr30000000stin3 qen3 stin3 qen2 stin3 qen1 stin3 qen0 stin3 smp1 stin3 smp0 stin3 dr2 stin3 dr1 stin3 dr0 sicr40000000stin4 qen3 stin4 qen2 stin4 qen1 stin4 qen0 stin4 smp1 stin4 smp0 stin4 dr2 stin4 dr1 stin4 dr0 sicr50000000stin5 qen3 stin5 qen2 stin5 qen1 stin5 qen0 stin5 smp1 stin5 smp0 stin5 dr2 stin5 dr1 stin5 dr0 sicr60000000stin6 qen3 stin6 qen2 stin6 qen1 stin6 qen0 stin6 smp1 stin6 smp0 stin6 dr2 stin6 dr1 stin6 dr0 sicr70000000stin7 qen3 stin7 qen2 stin7 qen1 stin7 qen0 stin7 smp1 stin7 smp0 stin7 dr2 stin7 dr1 stin7 dr0 stin#smp1-0 sampling point 00 3/4 point 01 4/4 point 10 1/4 point 11 2/4 point stin#dr2-0 data rate 000 disabled - external pull-up or pull-down is required for st-bus input 001 2.048 mbps 010 4.096 mbps 011 8.192 mbps 100 - 111 reserved
zl50010 data sheet 60 zarlink semiconductor inc. bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8stin#qen3 quadrant frame 3 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch24 to 31, ch48 to 63 and ch96 to 127 for the 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively. 7stin#qen2 quadrant frame 2 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch16 to 23, ch32 to 47 and ch64 to 95 for the 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively. 6stin#qen1 quadrant frame 1 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch8 to 15, ch16 to 31 and ch32 to 63 for the 2.048 mbps, 4.096 mbps and 8.192 mbps mode respectively. 5stin#qen0 quadrant frame 0 enable. when this bit is low, the device is in normal operation mode. when this bit is hi gh, the lsb of every channel in this quadrant frame is replaced by "1". this quadrant frame is defined as ch0 to 7, ch0 to 15 and ch0 to 31 for 2.048 mbps, the 4.096 mbps and 8.192 mbps mode respectively. table 26 - stream input control register 8 to 15 (sicr8 to sicr15) external read/write address: 110 h , 112 h , 114 h , 116 h , 118 h , 11a h , 11c h , 11e h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sicr8 0 0 0 0 0 0 0 stin8 qen3 stin8 qen2 stin8 qen1 stin8 qen0 stin8 smp1 stin8 smp0 stin8 dr2 stin8 dr1 stin8 dr0 sicr9 0 0 0 0 0 0 0 stin9 qen3 stin9 qen2 stin9 qen1 stin9 qen0 stin9 smp1 stin9 smp0 stin9 dr2 stin9 dr1 stin9 dr0 sicr10 0 0 0 0 0 0 0 stin10 qen3 stin10 qen2 stin10 qen1 stin10 qen0 stin10 smp1 stin10 smp0 stin10 dr2 stin10 dr1 stin10 dr0 sicr11 0 0 0 0 0 0 0 stin11 qen3 stin11 qen2 stin11 qen1 stin11 qen0 stin11 smp1 stin11 smp0 stin11 dr2 stin11 dr1 stin11 dr0 sicr12 0 0 0 0 0 0 0 stin12 qen3 stin12 qen2 stin12 qen1 stin12 qen0 stin12 smp1 stin12 smp0 stin12 dr2 stin12 dr1 stin12 dr0 sicr13 0 0 0 0 0 0 0 stin13 qen3 stin13 qen2 stin13 qen1 stin13 qen0 stin13 smp1 stin13 smp0 stin13 dr2 stin13 dr1 stin13 dr0 sicr14 0 0 0 0 0 0 0 stin14 qen3 stin14 qen2 stin14 qen1 stin14 qen0 stin14 smp1 stin14 smp0 stin14 dr2 stin14 dr1 stin14 dr0 sicr15 0 0 0 0 0 0 0 stin15 qen3 stin15 qen2 stin15 qen1 stin15 qen0 stin15 smp1 stin15 smp0 stin15 dr2 stin15 dr1 stin15 dr0
zl50010 data sheet 61 zarlink semiconductor inc. 4 - 3 stin#smp1 - 0 input data sampling point selection bits : 2 - 0 stin#dr2 - 0 input data rate selection bits: note: # denotes input stream from 8 to 15 bit name description table 26 - stream input control register 8 to 15 (sicr8 to sicr15) (continued) external read/write address: 110 h , 112 h , 114 h , 116 h , 118 h , 11a h , 11c h , 11e h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sicr8 0 0 0 0 0 0 0 stin8 qen3 stin8 qen2 stin8 qen1 stin8 qen0 stin8 smp1 stin8 smp0 stin8 dr2 stin8 dr1 stin8 dr0 sicr9 0 0 0 0 0 0 0 stin9 qen3 stin9 qen2 stin9 qen1 stin9 qen0 stin9 smp1 stin9 smp0 stin9 dr2 stin9 dr1 stin9 dr0 sicr10 0 0 0 0 0 0 0 stin10 qen3 stin10 qen2 stin10 qen1 stin10 qen0 stin10 smp1 stin10 smp0 stin10 dr2 stin10 dr1 stin10 dr0 sicr11 0 0 0 0 0 0 0 stin11 qen3 stin11 qen2 stin11 qen1 stin11 qen0 stin11 smp1 stin11 smp0 stin11 dr2 stin11 dr1 stin11 dr0 sicr12 0 0 0 0 0 0 0 stin12 qen3 stin12 qen2 stin12 qen1 stin12 qen0 stin12 smp1 stin12 smp0 stin12 dr2 stin12 dr1 stin12 dr0 sicr13 0 0 0 0 0 0 0 stin13 qen3 stin13 qen2 stin13 qen1 stin13 qen0 stin13 smp1 stin13 smp0 stin13 dr2 stin13 dr1 stin13 dr0 sicr14 0 0 0 0 0 0 0 stin14 qen3 stin14 qen2 stin14 qen1 stin14 qen0 stin14 smp1 stin14 smp0 stin14 dr2 stin14 dr1 stin14 dr0 sicr15 0 0 0 0 0 0 0 stin15 qen3 stin15 qen2 stin15 qen1 stin15 qen0 stin15 smp1 stin15 smp0 stin15 dr2 stin15 dr1 stin15 dr0 stin#smp1-0 sampling point 00 3/4 point 01 4/4 point 10 1/4 point 11 2/4 point stin#dr2-0 data rate 000 disabled - external pull-up or pull-down is required for st-bus input 001 2.048 mbps 010 4.096 mbps 011 8.192 mbps 100 - 111 reserved
zl50010 data sheet 62 zarlink semiconductor inc. table 27 - stream input delay register 0 to 7 (sidr0 to sidr7) bit name description 15 - 10 unused reserved. in normal functional mode, these bits must be set to zero. 9 - 3 stin#cd6 - 0 input stream# channel delay bits: the binary value of these bits refers to the number of channels that the input stream will be delayed. this value should not exceed the maximum channel number of the stream. zero means no delay. 2 - 0 stin#bd2 - 0 input stream# bit delay bits: the binary value of these bits refers to the number of bits that the input stream will be delayed. this maximum value is 7. zero means no delay. note: # denotes input stream from 0 to 7 external read/write address: 101 h , 103 h , 105 h , 107 h , 109 h , 10b h , 10d h , 10f h , reset value: 0000 h 1514131211109876543210 sidr0 0 0 0 0 0 0 stin0 cd6 stin0 cd5 stin0 cd4 stin0 cd3 stin0 cd2 stin0 cd1 stin0 cd0 stin0 bd2 stin0 bd1 stin0 bd0 sidr1 0 0 0 0 0 0 stin1 cd6 stin1 cd5 stin1 cd4 stin1 cd3 stin1 cd2 stin1 cd1 stin1 cd0 stin1 bd2 stin1 bd1 stin1 bd0 sidr2 0 0 0 0 0 0 stin2 cd6 stin2 cd5 stin2 cd4 stin2 cd3 stin2 cd2 stin2 cd1 stin2 cd0 stin2 bd2 stin2 bd1 stin2 bd0 sidr3 0 0 0 0 0 0 stin3 cd6 stin3 cd5 stin3 cd4 stin3 cd3 stin3 cd2 stin3 cd1 stin3 cd0 stin3 bd2 stin3 bd1 stin3 bd0 sidr4 0 0 0 0 0 0 stin4 cd6 stin4 cd5 stin4 cd4 stin4 cd3 stin4 cd2 stin4 cd1 stin4 cd0 stin4 bd2 stin4 bd1 stin4 bd0 sidr5 0 0 0 0 0 0 stin5 cd6 stin5 cd5 stin5 cd4 stin5 cd3 stin5 cd2 stin5 cd1 stin5 cd0 stin5 bd2 stin5 bd1 stin5 bd0 sidr6 0 0 0 0 0 0 stin6 cd6 stin6 cd5 stin6 cd4 stin6 cd3 stin6 cd2 stin6 cd1 stin6 cd0 stin6 bd2 stin6 bd1 stin6 bd0 sidr7 0 0 0 0 0 0 stin7 cd6 stin7 cd5 stin7 cd4 stin7 cd3 stin7 cd2 stin7 cd1 stin7 cd0 stin7 bd2 stin7 bd1 stin7 bd0
zl50010 data sheet 63 zarlink semiconductor inc. table 28 - stream input delay register 8 to 15 (sidr8 to sidr15) bit name description 15 - 10 unused reserved. in normal functional mode, these bits must be set to zero. 9 - 3 stin#cd6 - 0 input stream# channel delay bits: the binary value of these bits refers to the number of channels that the input stream will be delayed. this value should not exceed the maximum channel number of the stream. zero means no delay. 2 - 0 stin#bd2 - 0 input stream# bit delay bits: the binary value of these bits refers to the number of bits that the input stream will be delayed. this maximum value is 7. zero means no delay. note: # denotes input stream from 8 to 15 external read/write address: 111 h , 113 h , 115 h , 117 h , 119 h , 11b h , 11d h , 11f h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sidr8000000stin8 cd6 stin8 cd5 stin8 cd4 stin8 cd3 stin8 cd2 stin8 cd1 stin8 cd0 stin8b bd2 stin8b bd1 stin8b bd0 sidr9000000stin9 cd6 stin9 cd5 stin9 cd4 stin9 cd3 stin9 cd2 stin9 cd1 stin9 cd0 stin9b bd2 stin9b bd1 stin9b bd0 sidr10000000stin10 cd6 stin10 cd5 stin10 cd4 stin10 cd3 stin10 cd2 stin10 cd1 stin10 cd0 stin10 bd2 stin10 bd1 stin10 bd0 sidr11000000stin11 cd6 stin11 cd5 stin11 cd4 stin11 cd3 stin11 cd2 stin11 cd1 stin11 cd0 stin11 bd2 stin11 bd1 stin11 bd0 sidr12 0 0 0 0 00stin12 cd6 stin12 cd5 stin12 cd4 stin12 cd3 stin12 cd2 stin12 cd1 stin12 cd0 stin12 bd2 stin12 bd1 stin12 bd0 sidr13000000stin13 cd6 stin13 cd5 stin13 cd4 stin13 cd3 stin13 cd2 stin13 cd1 stin13 cd0 stin13 bd2 stin13 bd1 stin13 bd0 sidr14000000stin14 cd6 stin14 cd5 stin14 cd4 stin14 cd3 stin14 cd2 stin14 cd1 stin14 cd0 stin14 bd2 stin14 bd1 stin14 bd0 sidr15000000stin15 cd6 stin15 cd5 stin15 cd4 stin15 cd3 stin15 cd2 stin15 cd1 stin15 cd0 stin15 bd2 stin15 bd1 stin15 bd0
zl50010 data sheet 64 zarlink semiconductor inc. table 29 - stream output control register 0 to 7 (socr0 to socr7) bit name description 15 - 7 unused reserved. in normal functional mode, these bits must be set to zero. 6stohz#ac stohz advancement control. when this bit is low, the advancement unit is 15.2 ns. when this bit is high, the advancement unit is 1/4 bit. 5 - 3 stohz#a2 - 0 stohz additional advancement bits : 2 - 0 sto#dr2 - 0 output data rate selection bits: note: # denotes input stream from 0 to 7 external read/write address: 200 h , 202 h , 204 h , 206 h , 208 h , 20a h , 20c h , 20e h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 43210 socr0 0 0 0 0 0 0 0 0 0 stohz0 ac stohz0 a2 stohz0 a1 stohz0 a0 sto0 dr2 sto0 dr1 sto0 dr0 socr1 0 0 0 0 0 0 0 0 0 stohz1 ac stohz1 a2 stohz1 a1 stohz1 a0 sto1 dr2 sto1 dr1 sto1 dr0 socr2 0 0 0 0 0 0 0 0 0 stohz2 ac stohz2 a2 stohz2 a1 stohz2 a0 sto2 dr2 sto2 dr1 sto2 dr0 socr3 0 0 0 0 0 0 0 0 0 stohz3 ac stohz3 a2 stohz3 a1 stohz3 a0 sto3 dr2 sto3 dr1 sto3 dr0 socr4 0 0 0 0 0 0 0 0 0 stohz4 ac stohz4 a2 stohz4 a1 stohz4 a0 sto4 dr2 sto4 dr1 sto4 dr0 socr5 0 0 0 0 0 0 0 0 0 stohz5 ac stohz5 a2 stohz5 a1 stohz5 a0 sto5 dr2 sto5 dr1 sto5 dr0 socr6 0 0 0 0 0 0 0 0 0 stohz6 ac stohz6 a2 stohz6 a1 stohz6 a0 sto6 dr2 sto6 dr1 sto6 dr0 socr7 0 0 0 0 0 0 0 0 0 stohz7 ac stohz7 a2 stohz7 a1 stohz7 a0 sto7 dr2 sto7 dr1 sto7 dr0 stohz#a2-0 additional advancement (stohz#ac = 0) additional advancement (stohz#ac = 1) 000 0.0 ns 0 bit 001 15.2 ns 1/4 bit 010 30.5 ns 1/2 bit 011 45.7 ns 3/4 bit 100 61.0 ns 4/4 bit 101-111 reserved reserved sto#dr2-0 output data rate 000 sto hiz stohz driven high 001 2.048 mbps 010 4.096 mbps 011 8.192 mbps 100 - 111 reserved
zl50010 data sheet 65 zarlink semiconductor inc. table 30 - stream output control register 8 to 15 (socr8 to socr15) bit name description 15 - 7 unused reserved. in normal functional mode, these bits must be set to zero. 6stohz#ac stohz advancement control. when this bit is low, the advancement unit is 15.2 ns. when this bit is high, the advancement unit is 1/4 bit. 5 - 3 stohz#a2 - 0 stohz additional advancement bits : 2 - 0 sto#dr2 - 0 output data rate selection bits: note: # denotes input stream from 8 to 15 external read/write address: 210 h , 212 h , 214 h , 216 h , 218 h , 21a h , 21c h , 21e h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 43210 socr8000000000stohz8 ac stohz8 a2 stohz8 a1 stohz8 a0 sto8 dr2 sto8 dr1 sto8 dr0 socr9000000000stohz9 ac stohz9 a2 stohz9 a1 stohz9 a0 sto9 dr2 sto9 dr1 sto9 dr0 socr10000000000stohz10 ac stohz10 a2 stohz10 a1 stohz10 a0 sto10 dr2 sto10 dr1 sto10 dr0 socr11000000000stohz11 ac stohz11 a2 stohz11 a1 stohz11 a0 sto11 dr2 sto11 dr1 sto11 dr0 socr12000000000stohz12 ac stohz12 a2 stohz12 a1 stohz12 a0 sto12 dr2 sto12 dr1 sto12 dr0 socr13000000000stohz13 ac stohz13 a2 stohz13 a1 stohz13 a0 sto13 dr2 sto13 dr1 sto13 dr0 socr14000000000stohz14 ac stohz14 a2 stohz14 a1 stohz14 a0 sto14 dr2 sto14 dr1 sto14 dr0 socr15000000000stohz15 ac stohz15 a2 stohz15 a1 stohz15 a0 sto15 dr2 sto15 dr1 sto15 dr0 stohz#a2-0 additional advancement (stohz#ac = 0) additional advancement (stohz#ac = 1) 000 0.0 ns 0 bit 001 15.2 ns 1/4 bit 010 30.5 ns 1/2 bit 011 45.7 ns 3/4 bit 100 61.0 ns 4/4 bit 101-111 reserved reserved sto#dr2-0 output data rate 000 sto hiz stohz driven high 001 2.048 mbps 010 4.096 mbps 011 8.192 mbps 100 - 111 reserved
zl50010 data sheet 66 zarlink semiconductor inc. table 31 - stream output offset register 0 to 7 (soor0 to soor7) bit name description 15 - 12 unused reserved. 11 - 5 sto#cd6-0 output stream# channel delay bits: the binary value of these bits refers to the number of chann els that the output stream is to be advanced. this value should not exceed the maximum channel number of the stream. zero means no advancement. 4 - 2 sto#bd2-0 output stream# bit delay selection bits: the binary value of these bits refers to the number of bits t hat the output stream is to be advanced. the maximum value is 7. zero means no advancement. 1 - 0 sto#fa1-0 output stream# fractional advancement bits note: # denotes input stream from 0 to 7 external read/write address: 201 h , 203 h , 205 h , 207 h , 209 h , 20b h , 20d h , 20f h , reset value: 0000 h 1514131211109876543210 soor0 0 0 0 0 sto0 cd6 sto0 cd5 sto0 cd4 sto0 cd3 sto0 cd2 sto0 cd1 sto0 cd0 sto0 bd2 sto0 bd1 sto0 bd0 sto0 fa1 sto0 fa0 soor1 0 0 0 0 sto1 cd6 sto1 cd5 sto1 cd4 sto1 cd3 sto1 cd2 sto1 cd1 sto1 cd0 sto1 bd2 sto1 bd1 sto1 bd0 sto1 fa1 sto1 fa0 soor2 0 0 0 0 sto2 cd6 sto2 cd5 sto2 cd4 sto2 cd3 sto2 cd2 sto2 cd1 sto2 cd0 sto2 bd2 sto2 bd1 sto2 bd0 sto2 fa1 sto2 fa0 soor3 0 0 0 0 sto3 cd6 sto3 cd5 sto3 cd4 sto3 cd3 sto3 cd2 sto3 cd1 sto3 cd0 sto3 bd2 sto3 bd1 sto3 bd0 sto3 fa1 sto3 fa0 soor4 0 0 0 0 sto4 cd6 sto4 cd5 sto4 cd4 sto4 cd3 sto4 cd2 sto4 cd1 sto4 cd0 sto4 bd2 sto4 bd1 sto4 bd0 sto4 fa1 sto4 fa0 soor5 0 0 0 0 sto5 cd6 sto5 cd5 sto5 cd4 sto5 cd3 sto5 cd2 sto5 cd1 sto5 cd0 sto5 bd2 sto5 bd1 sto5 bd0 sto5 fa1 sto5 fa0 soor6 0 0 0 0 sto6 cd6 sto6 cd5 sto6 cd4 sto6 cd3 sto6 cd2 sto6 cd1 sto6 cd0 sto6 bd2 sto6 bd1 sto6 bd0 sto6 fa1 sto6 fa0 soor7 0 0 0 0 sto7 cd6 sto7 cd5 sto7 cd4 sto7 cd3 sto7 cd2 sto7 cd1 sto7 cd0 sto7 bd2 sto7 bd1 sto7 bd0 sto7 fa1 sto7 fa0 sto#fa1-0 advanced by 00 0 01 1/4 bit 10 2/4 bit 11 3/4 bit
zl50010 data sheet 67 zarlink semiconductor inc. table 32 - stream output offset register 8 to 15 (soor8 to soor15) bit name description 15 - 12 unused reserved. 11 - 5 sto#cd6-0 output stream# channel delay bits: the binary value of these bits refers to the number of chann els that the output stream is to be advanced. this value should not exceed the maximum channel number of the stream. zero means no advancement. 4 - 2 sto#bd2-0 output stream# bit delay selection bits: the binary value of these bits refers to the number of bits t hat the output stream is to be advanced. the maximum value is 7. zero means no advancement. 1 - 0 sto#fa1-0 output stream# fractional advancement bits note: # denotes input stream from 8 to 15 external read/write address: 211 h , 213 h , 215 h , 217 h , 219 h , 21b h , 21d h , 21f h , reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soor8 0 0 0 0 sto8c d6 sto8 cd5 sto8 cd4 sto8 cd3 sto8 cd2 sto8 cd1 sto8 cd0 sto8b bd2 sto8 bd1 sto8 bd0 sto8 fa1 sto8 fa0 soor9 0 0 0 0 sto9c d6 sto9 cd5 sto9 cd4 sto9 cd3 sto9 cd2 sto9 cd1 sto9 cd0 sto9 bd2 sto9 bd1 sto9 bd0 sto9 fa1 sto9 fa0 soor10 0 0 0 0 sto10 cd6 sto10 cd5 sto10 cd4 sto10 cd3 sto10 cd2 sto10 cd1 sto10 cd0 sto10 bd2 sto10 bd1 sto10 bd0 sto10 fa1 sto10 fa0 soor11 0 0 0 0 sto11 cd6 sto11 cd5 sto11 cd4 sto11 cd3 sto11 cd2 sto11 cd1 sto11 cd0 sto11 bd2 sto11 bd1 sto11 bd0 sto11 fa1 sto11 fa0 soor12 0 0 0 0 sto12 cd6 sto12 cd5 sto12 cd4 sto12 cd3 sto12 cd2 sto12 cd1 sto12 cd0 sto12 bd2 sto12 bd1 sto12 bd0 sto12 fa1 sto12 fa0 soor13 0 0 0 0 sto13 cd6 sto13 cd5 sto13 cd4 sto13 cd3 sto13 cd2 sto13 cd1 sto13 cd0 sto13 bd2 sto13 bd1 sto13 bd0 sto13 fa1 sto13 fa0 soor14 0 0 0 0 sto14 cd6 sto14 cd5 sto14 cd4 sto14 cd3 sto14 cd2 sto14 cd1 sto14 cd0 sto14 bd2 sto14 bd1 sto14 bd0 sto14 fa1 sto14 fa0 soor15 0 0 0 0 sto15 cd6 sto15 cd5 sto1 cd4 sto15 cd3 sto15 cd2 sto15 cd1 sto15 cd0 sto15 bd2 sto15 bd1 sto15 bd0 sto15 fa1 sto15 fa0 sto#fa1-0 advanced by 00 0 01 1/4 bit 10 2/4 bit 11 3/4 bit
zl50010 data sheet 68 zarlink semiconductor inc. 8.0 memory address mappings when a11 is high, the data or the connection memory can be accessed by the microprocessor port. the bit 0 to bit 2 in the control register determine the access to the data or connection memory msb (note 1) stream address (st. 0-15) channel address (ch 0-127) external address (a11) a10 a9 a8 a7 stream # a6a5a4a3a2a1a0 channel # 1 1 1 1 1 1 1 1 1 . . . . . 1 1 0 0 0 0 0 0 0 0 0 . . . . . 1 1 0 0 0 0 1 1 1 1 1 . . . . . 1 1 0 0 1 1 0 0 1 1 0 . . . . . 1 1 0 1 0 1 0 1 0 1 0 . . . . . 0 1 stream 0 stream 1 stream 2 stream 3 stream 4 stream 5 stream 6 stream 7 stream 8 . . . . . stream 14 stream 15 0 0 . . 0 0 0 0 . . 0 0 . . 1 1 0 0 . . 0 0 1 1 . . 1 1 . . 1 1 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 0 1 . . 0 1 0 1 . . 0 1 . . 0 1 ch 0 ch 1 . . ch 30 ch 31 (note 2) ch 32 ch 33 . . ch 62 ch 63 (note 3) . . ch 126 ch 127 (note 4) notes: 1. msb of address must be high for access to data and connection memory positions. msb must be low for access to registers. 2. channels 0 to 31 are used when serial stream is at 2.048 mbps. 3. channels 0 to 63 are used when serial stream is at 4.096 mbps. 4. channels 0 to 127 are used when serial stream is at 8.192 mbps. table 33 - address map for memory locations (512x512 dx, msb of address = 1)
zl50010 data sheet 69 zarlink semiconductor inc. 9.0 connection memory bit assignment when the cmm bit (bit0) is zero, the connection is in normal switching mode. when the cmm bit is one, the connection memory is in special transmission mode. table 34 - connection memory bit assignment when the cmm bit = 0 table 35 - connection memory bits assignment when the cmm bit = 1 bit name description 11 - 8 ssa3-0 source stream address. the binary value of these 4 bits re presents the input stream number. 7 - 1 sca6-0 source channel address. the binary value of these 7 bits represents the input channel number. 0 cmm=0 connection memory mode = 0. if this bit is set low, the connection memory is in normal switching mode. bit 1 to 11 represent the source str eam number and channel number. bit name description 11 unused reserved. 10 - 3 msg7-0 message data bits: 8 bit data for the message mode. 2 - 1 pcc1-0 per-channel control bits: these two bits control outputs . 0 cmm=1 connection memory mode = 1. if this bit is set high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel message mode or per-channel ber mode. 1110987654321 0 ssa3 ssa2 ssa1 ssa0 sca6 sca5 sca4 sca3 sca2 sca1 sca0 cmm =0 1110987654321 0 0 msg7 msg6 msg5 msg4 msg3 msg2 msg1 msg0 pcc1 pcc0 cmm =1 pcc pcc0 output 0 0 per channel tristate 0 1 message mode 1 0 ber test mode 11 reserved
zl50010 data sheet 70 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. * note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage ( v in ). absolute maximum ratings* parameter symbol min. max. units 1 i/o supply voltage v dd -0.5 5.0 v 2 input voltage v i_3v -0.5 v dd + 0.5 v 3 input voltage (5 v tolerant inputs) v i_5v -0.5 7.0 v 4 continuous current at digital outputs i o 15 ma 5 package power dissipation p d 0.75 w 6 storage temperature t s - 55 +125 c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated . characteristics sym. min. typ. ? max. units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd 3.0 3.3 3.6 v 3 input voltage v i 0v dd v 4 input voltage on 5 v tolerant inputs v i_5v 05.5v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply current i dd 250 ma output unloaded 2 input high voltage v ih 2.0 v 3 input low voltage v il 0.8 v 4 input leakage (input pins) input leakage (bi-di rectional pins) i il i bl 5 5 a a 0 zl50010 data sheet 71 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - timing parameter measurement voltage levels characteristics sym. level units conditions 1 cmos threshold v ct 0.5v dd_io v 2 rise/fall threshold voltage high v hm 0.7v dd_io v 3 rise/fall threshold voltage low v lm 0.3v dd_io v ac electrical characteristics ? - fpi and cki timing when ckin2 to 0 bits = 000 characteristic sym. min. typ. ? max. units notes 1fpi input frame pulse width t fpiw 40 61 115 ns 2fpi input frame pulse setup time t fpis 20 40 ns 3fpi input frame pulse hold time t fpih 20 40 ns 4cki input clock period t ckip 55 61 67 ns 5cki input clock high time t ckih 27 33 ns 6cki input clock low time t ckil 27 33 ns 7cki input clock rise/fall time t rcki , t fcki 03ns ac electrical characteristics ? - fpi and cki timing when ckin2 to 0 bits = 001 characteristic sym. min. typ. ? max. units notes 1fpi input frame pulse width t fpiw 90 122 220 ns 2fpi input frame pulse setup time t fpis 45 90 ns 3fpi input frame pulse hold time t fpih 45 90 ns 4cki input clock period t ckip 110 122 135 ns 5cki input clock high time t ckih 63 69 ns 6cki input clock low time t ckil 63 69 ns 7cki input clock rise/fall time t rcki , t fcki 03ns ac electrical characteristics - fpi and cki timing when ckin2 to 0 bits = 010 characteristic sym. min. typ. ? max. units notes 1fpi input frame pulse width t fpiw 90 244 420 ns 2fpi input frame pulse setup time t fpis 110 135 ns 3fpi input frame pulse hold time t fpih 120 145 ns 4cki input clock period t ckip 220 244 270 ns 5cki input clock high time t ckih 110 135 ns 6cki input clock low time t ckil 110 135 ns 7cki input clock rise/fall time t rcki , t fcki 03ns
zl50010 data sheet 72 zarlink semiconductor inc. figure 33 - frame pulse input and clock input timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 34 - frame boundary timing with input clock (cycle-to-cycle) variation ac electrical characteristics ? - frame boundary timing with input clock cycle-to-cycle variation characteristic sym. min. typ. ? max. units notes 1 cki input clock cycle-to-cycle variation t ckv 050ns t fpiw fpi t fph t ckil t ckih t fpis t ckip cki input frame boundary cki fpi t ckv t ckv input frame boundary n input frame boundary n + 1
zl50010 data sheet 73 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 35 - frame boundary timing with i nput frame pulse (cycle-to-cycle) variation ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 36 - xtali input timing diagram when clock oscillator is connected ac electrical characteristics ? - frame boundary timing with input frame pulse cycle-to- cycle variation characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse cyc le-to-cycle variation t fpv 050ns ac electrical characteristics ? - xtali input timing when clock oscillator is connected characteristic sym. min. typ. ? max. units notes 1 c20i input clock period t c20mp 49.995 50 50.005 ns 2 c20i input clock high time t c20mh 20 30 ns 3 c20i input clock low time t c20ml 20 30 ns 4 c20i input rise/fall time t rc20m , t fc20m 2ns cki fpi t fpv input frame boundary n input frame boundary n + 1 t fpv xtali t fc20m t c20ml t c20mh t rc20m t c20mp
zl50010 data sheet 74 zarlink semiconductor inc. ac electrical characteristics - reference input timing figure 37 - reference input timing diagram when the input frequency = 8 khz figure 38 - reference input timing diagram when the input frequency = 2.048 mhz figure 39 - reference input timing diag ram when the input frequency = 1.544 hz characteristic sym. min. typ. max. units notes 1 pri_ref, sec_ref period t r8kp 122 125 128 s 8khz mode 2 pri_ref, sec_ref high time t r8kh 0.09 127.91 s 3 pri_ref, sec_ref low time t r8kl 0.09 127.91 s 4 pri_ref, sec_ref rise/fall time t rr8k, t f r8k 020ns 5 pri_ref, sec_ref period t r2mp 370 488 605 ns 2.048 mhz mode 6 pri_ref, sec_ref high time t r2mh 90 244 515 ns 7 pri_ref, sec_ref low time t r2ml 90 244 515 ns 8 pri_ref, sec_ref rise/fall time t rr2m, t fr2m 020ns 9 pri_ref, sec_ref period t r1m5p 490 648 805 ns 1.544 mhz mode 10 pri_ref, sec_ref high time t r1m5h 90 324 715 ns 11 pri_ref, sec_ref low time t r1m5l 90 324 715 ns 12 pri_ref, sec_ref rise/fall time t rr1m5 , t fr1m5 020ns pri_ref, t fk8k t rr8k t r8kl t r8kh t r8kp (8 khz) sec_ref pri_ref, t fr2m t rr2m t r2mp t r2ml t r2mh (2.048 mhz) sec_ref t fr1m5 t rr1m5 t r1m5p t r1m5l t r1m5h (1.544 mhz) pri_ref, sec_ref
zl50010 data sheet 75 zarlink semiconductor inc. ac electrical characteristics - input and output frame boundary alignment figure 40 - input and out put frame boundary offset characteristic sym. min. typ max. units notes 1 input and output frame offset in dpll master mode t fbos -20 0 ns input reference is internal 8 khz derived from fpi and cki . measured when there is no jitter on the cki and fpi inputs. 2 input and output frame offset in dpll bypass mode t fbos 1 18 ns measured when there is no jitter on the cki and fpi inputs. cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) input frame boundary cko2 or fpo1 fpo2 or fpo1 (16.384 mhz) cko1 or cko0 fpo1 or fpo0 (8.192 mhz) cko0 fpo0 (4.096 mhz) cko2 fpo2 (32.768 mhz) output frame boundary t fbos
zl50010 data sheet 76 zarlink semiconductor inc. ac electrical characteristics ? - fpo0 and cko0 timing when ckfp0 = 0 ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - fpo0 and cko0 timing when ckfp0 = 1 ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 41 - fpo0 and cko0 timing diagram characteristic sym. min. typ. ? max. units notes 1fpo0 output pulse width t fpw0 220 244 270 ns c l =30pf 2fpo0 output delay from the cko0 falling edge to the output frame boundary t fodf0 115 130 ns 3fpo0 output delay from the output frame boundary to the cko0 rising edge t fodr0 115 130 ns 4cko0 output clock period t ckp0 220 244 270 ns c l =30pf 5cko0 output high time t ckh0 115 130 ns 6cko0 output low time t ckl0 115 130 ns 7cko0 output rise/fall time t rck0 , t fck0 10 ns characteristic sym. min. typ. ? max. units notes 1fpo0 output pulse width t fpw0 108 122 140 ns c l =30 pf 2fpo0 output delay from the cko0 falling edge to the output frame boundary t fodf0 54 68 ns 3fpo0 output delay from the output frame boundary to the cko0 rising edge t fodr0 54 68 ns 4cko0 output clock period t ckp0 108 122 140 ns c l =30 pf 5cko0 output high time t ckh0 54 69 ns 6cko0 output low time t ckl0 54 69 ns 7cko0 output rise/fall time t rck0 , t fck0 10 ns t fpw0 t fodr0 t fodf0 fpo0 cko0 t ckl0 t ckh0 t ckp0 t rck0 t fck0 output frame boundary v tt v tt
zl50010 data sheet 77 zarlink semiconductor inc. ac electrical characteristics ? - fpo1 and cko1 timing when ckfp1 = 0 ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - fpo1 and cko1 timing when ckfp1 = 1 ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 42 - fpo1 and cko1 timing diagram characteristic sym. min. typ. ? max. units notes 1fpo1 output pulse width t fpw1 47 61 75 ns c l =30 pf 2fpo1 output delay from the cko1 falling edge to the output frame boundary t fodf1 20 40 ns 3fpo1 output delay from the output frame boundary to the cko1 rising edge t fodr1 20 40 ns 4cko1 output clock period t ckp1 47 61 75 ns c l =30 pf 5cko1 output high time t ckh1 20 40 ns 6cko1 output low time t ckl1 20 40 ns 7cko1 output rise/fall time t rck1 , t fck1 10 ns characteristic sym. min. typ. ? max. units notes 1fpo1 output pulse width t fpw1 108 122 140 ns c l =30 pf 2fpo1 output delay from the cko1 falling edge to the output frame boundary t fodf1 54 68 ns 3fpo1 output delay from the output frame boundary to the cko1 rising edge t fodr1 54 68 ns 4cko1 output clock period t ckp1 108 122 140 ns c l =30 pf 5cko1 output high time t ckh1 54 69 ns 6cko1 output low time t ckl1 54 69 ns 7cko1 output rise/fall time t rck1 , t fck1 10 ns t fpw1 t fodr1 t fodf1 fpo1 cko1 t ckl1 t ckh1 t ckp1 t rck1 t fck1 output frame boundary v tt v tt
zl50010 data sheet 78 zarlink semiconductor inc. ac electrical characteristics ? - fpo2 and cko2 timing when ckfp2 = 0 ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - fpo2 and cko2 timing when ckfp2 = 1 ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 43 - fpo2 and cko2 timing diagram characteristic sym. min. typ. ? max. units notes 1fpo2 output pulse width t fpw2 15 30 45 ns c l =30 pf 2fpo2 output delay from the cko2 falling edge to the output frame boundary t fodf2 822ns 3fpo2 output delay from the output frame boundary to the cko2 rising edge t fodr2 822ns 4cko2 output clock period t ckp2 15 30 45 ns c l =30 pf 5cko2 output high time t ckh2 822ns 6cko2 output low time t ckl2 822ns 7cko2 output rise/fall time t rck2 , t fck2 7ns characteristic sym. min. typ. ? max. units notes 1fpo2 output pulse width t fpw2 47 61 75 ns c l =30 pf 2fpo2 output delay from the cko2 falling edge to the output frame boundary t fodf2 20 40 ns 3fpo2 output delay from the output frame boundary to the cko2 rising edge t fodr2 20 40 ns 4cko2 output clock period t ckp2 47 61 75 ns c l =30 pf 5cko2 output high time t ckh2 20 40 ns 6cko2 output low time t ckl2 20 40 ns 7cko2 output rise/fall time t rck2 , t fck2 10 ns t fpw2 t fodr2 t fodf2 fpo2 cko2 t ckl2 t ckh2 t ckp2 t rck2 t fck2 output frame boundary v tt v tt
zl50010 data sheet 79 zarlink semiconductor inc. ac electrical characteristics ? - st-bus input timing ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 44 - st-bus inputs (sti0 - 15) timing diagram characteristic sym. min. typ. ? max. units test conditions 1 sti setup time 2.048 mbps 4.096 mbps 8.192 mbps t sis2 t sis4 t sis8 3 3 3 ns ns ns 2sti hold time 2.048 mbps 4.096 mbps 8.192 mbps t sih2 t sih4 t sih8 3 3 3 ns ns ns v tt cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) t sis2 t sih2 bit7 ch0 bit6 ch0 t sis4 t sih4 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit0 ch63 bit7 ch0 bit0 ch127 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit1 ch127 8.192 mbps 4.096 mbps 2.048 mbps t sis8 t sih8 input frame boundary sti0 - 15 sti0 - 15 sti0 - 15 v tt v tt bit0 ch31 v tt
zl50010 data sheet 80 zarlink semiconductor inc. ac electrical characteristics ? - st-bus output timing ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 45 - st-bus outputs (sto0 - 15) timing diagram characteristic sym. min. typ. ? max. units test conditions 1 sto delay - active to active @2.048 mbps @4.096 mbps @8.192 mbps t sod2 t sod4 t sod8 10 10 10 ns ns ns c l = 30 pf cko2 or fpo1 fpo2 or fpo1 (16.384 mhz) cko1 or cko0 fpo1 or fpo0 (8.192 mhz) cko0 fpo0 (4.096 mhz) 8.192 mbps 4.096 mbps 2.048 mbps output frame boundary sto0 - 15 sto0 - 15 sto0 - 15 bit7 ch0 bit7 ch0 bit7 ch0 bit7 ch0 bit7 ch63 bit7 ch0 bit7 ch0 bit7 ch31 t sod2 t sod4 t sod8 v tt v tt v tt bit0 ch127 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 cko2 fpo2 (32.768 mhz)
zl50010 data sheet 81 zarlink semiconductor inc. ac electrical characteristics ? - st-bus output tristate timing ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel the time taken to discharge c l . figure 46 - serial output and external control figure 47 - output driver enable (ode) characteristic sym. min. typ. ? max. units test conditions 1 sto delay - active to high-z sto delay - high-z to active 2.048 mbps 4.096 mbps 8.192 mbps t dz, t zd 15 15 15 ns ns ns r l =1 k, c l =30 pf, see note 1. 2 output driver enable (ode) delay - high-z to active 2.048 mbps 4.096 mbps 8.192 mbps t zd_ode 45 45 45 ns ns ns 2 output driver disable (ode) delay - active to high-z 2.048 mbps 4.096 mbps 8.192 mbps t dz_ode 30 30 30 ns ns ns t dz sto t zd sto cko0-2 v tt v tt tri-state valid data v tt tri-state valid data v tt hiz hiz sto ode t zd_ode valid data v tt t dz_ode
zl50010 data sheet 82 zarlink semiconductor inc. ac electrical characteristics - motorola non-multiplexed bus mode figure 48 - motorola non-multiplexed bus timing characteristics sym. min. typ . max. units test conditions 2 1cs setup from ds falling t css 0ns 2r/w setup from ds falling t rws 10 ns 3 address setup from ds falling t ads 5ns 4ds delay from the rising edge of dta to the falling edge of the ds t dsd 50 ns 5cs delay from the rising edge of dta to the falling edge of the cs t csd 50 ns 6cs hold after ds rising t csh 0ns 7r/w hold after ds rising t rwh 0ns 8 address hold after ds rising t adh 0ns 9 data setup from dta low on read t ddr 20 ns c l =30 pf 10 data hold on read t dhr 39nsc l =30 pf, r l =1 k (note 1) 11 data setup from ds falling on write t wds 10 ns 12 data hold on write t dhw 0ns 13 acknowledgment delay: reading/writing registers reading/writing memory t akd 120/105 200/150 ns ns c l =30 pf c l =30 pf 14 acknowledgment hold time t akh 20 ns c l =30 pf, r l =1 k (note 1) note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 600 microseconds must be applied befo re the first microprocessor access is performed after the reset pin is set high. ds a0-a11 cs d0-d15 d0-d15 read write t csh t adh t dhr t rws r/w t ads t rwh t dhw t akd t wds t ddr t akh dta v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data t css t csd t dsd
zl50010 data sheet 83 zarlink semiconductor inc. ac electrical characteristics ? - jtag test port and reset pin timing ?characteristics are over recommended operating conditions unless otherwise stated. figure 49 - jtag test port timing diagram figure 50 - reset pin timing diagram characteristic sym. min. typ. max. units notes 1 tck clock period t tckp 100 ns 2 tck clock pulse width high t tckh 80 ns 3 tck clock pulse width low t tckl 80 ns 4 tms set-up time t tmss 10 ns 5 tms hold time t tmsh 10 ns 6 tdi input set-up time t tdis 20 ns 7 tdi input hold time t tdih 60 ns 8 tdo output delay t tdod 25 ns c l =30 pf 9trst pulse width t trstw 200 ns 10 reset pulse width t rstw 1.0 ms t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst t rstw reset
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes 213740 1 15nov02 2 213834 11dec02
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